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Part: SN74ABT16657DLR
Category:
Logic
-> Transceivers
-> Parity Transceivers
Description: ti SN74ABT16657, 16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN74ABT16657DLR datasheet File size : 214 kB
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Datasheet text preview:
SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS103B FEBRUARY 1992 REVISED JANUARY 1997
D D D D D D D D
Members of the Texas Instruments WidebusTM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16657 . . . WD PACKAGE SN74ABT16657 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT16657 contain two noninverting octal transceiver sections with separate parity generator/checker circuits and control signals. For either section, the transmit/receive (1T/R or 2T/R) input determines the direction of data flow. When 1T/R (or 2T/R) is high, data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmit mode); when 1T/R (or 2T/R) is low, data flows from the 1B (or 2B) port to the 1A (or 2A) port (receive mode). When the output-enable (1OE or 2OE) input is high, both the 1A (or 2A) and 1B (or 2B) ports are in the high-impedance state.
1OE NC 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR NC 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1T/R 1ODD/EVEN 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2ODD/EVEN 2T/R
NC No internal connection
Odd or even parity is selected by a logic high or low level, respectively, on the 1ODD/EVEN (or 2ODD/EVEN) input. 1PARITY (or 2PARITY) carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or 2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or 2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus bits plus parity bit) are high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS103B FEBRUARY 1992 REVISED JANUARY 1997
description (continued)
In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if 1ODD/EVEN is high (odd parity selected), 1PARITY is high, and there are three high bits on the 1B bus, then 1ERR is low, indicating a parity error. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16657 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16657 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 8-bit section) NUMBER OF A OR B INPUTS THAT ARE HIGH INPUTS OE L L 0, 2 4, 6 8 2, 4 6, L L L L L L 1, 3 5 7 3, 5, L L L L Don't care H T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X INPUT/OUTPUT PARITY H L H L H L L H H L H L Z OUTPUTS ERR Z Z H L L H Z Z L H H L Z OUTPUT MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS103B FEBRUARY 1992 REVISED JANUARY 1997
logic symbol
1OE 1T/R 1ODD/EVEN 2OE 2T/R 2ODD/EVEN 1A1 1 56 55 28 29 30 G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 G8 8 EN6/8G10 [REC] 8 EN7 [XMIT] N9 1 Z11 1 1 2 51 49 48 47 45 44 43 11 · · · 15 18 6 Z21 1 1 7 41 40 38 37 36 34 33 21 · · · 28 2k 9, 7 10 26 9, 6 31 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2PARITY 2k 4, 2 5 3 4, 1 42 1ERR 2B1 54 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1PARITY 52 1B1
5
1A2 1A3 1A4 1A5 1A6 1A7 1A8
6 8 9 10 12 13 14
2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
16 17 19 20 21 23 24
2ERR
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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