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Part: SN74ABT16823DGG
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: 18-bit Bus-interface Flip-flops With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN74ABT16823DGG datasheet File size : 214 kB
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Datasheet text preview:
SN54ABT16823, SN74ABT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS217C JUNE 1992 REVISED JANUARY 1997
D D D D D D D D D
Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation High-Impedance State During Power Up and Power Down ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL ) Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16823 . . . WD PACKAGE SN74ABT16823 . . . DGG OR DL PACKAGE (TOP VIEW)
description
These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.
1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1CLKEN 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2CLKEN 2CLK
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN54ABT16823, SN74ABT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS217C JUNE 1992 REVISED JANUARY 1997
description (continued)
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16823 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 9-bit flip-flop) INPUTS OE L L L L L H CLR L H H H H X CLKEN X L L L H X CLK X L X X D X H L X X X OUTPUT Q L H L Q0 Q0 Z
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16823, SN74ABT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS217C JUNE 1992 REVISED JANUARY 1997
logic symbol
2 1OE 1CLR 1CLKEN 1CLK 2OE 2CLR 2CLKEN 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 56 27 28 30 29 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 8D 5, 6 1 55 EN1 R2 G3 3C4 EN5 R6 G7 7C8 4D 1, 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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