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Details, datasheet, quote on part number:SN74ABT16833DLR
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Datasheet text preview:
SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D FEBRUARY 1991 REVISED JANUARY 1997
D D D D D D D D D D
Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL) Parity-Error Flag With Parity Generator/Checker Register for Storage of Parity-Error Flag Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16833 . . . WD PACKAGE SN74ABT16833 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.
1OEB 1CLK 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR 2CLK 2OEB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEA 1CLR 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2CLR 2OEA
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR) is cleared (set high) by taking the clear (1CLR or 2CLR) input low. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D FEBRUARY 1991 REVISED JANUARY 1997
description (continued)
The SN54ABT16833 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16833 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEB L H X OEA H L X CLR X H L H H H L H H L L X CLK X X No No X Ai OF H Odd Even NA X X X Odd Even Odd Even NA NA A H L X Z Z Z Bi OF H NA Odd Even X A NA B X OUTPUT AND I/O B A NA NA PARITY L H NA NA ERR NA H L H NC H H L NA A data to B bus and generate inverted parity Isolation§ FUNCTION A data to B bus and generate parity B data to A bus and check parity Check error-flag register
NA = not applicable, NC = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS097D FEBRUARY 1991 REVISED JANUARY 1997
logic symbol
PARITY XCVR SN74ABT16833 1CLK 1CLR 1OEA 1OEB 2CLK 2CLR 2OEA 2OEB 2PARITY 31 2PARITY 2ERR 26 2ERR 1PARITY 54 1PARITY 1ERR 3 1ERR
1CLK 1CLR 1OEA 1OEB 2CLK 2CLR 2OEA 2OEB
2 55 56 1 27 30 29 28
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24
1
1
52 51 49 48
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
A Bus
B Bus
47 45 44
8 1
8 1
43 42 41 40 38
A Bus
B Bus
37 36 34
8
8
33
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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