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Part: SN74ABT16843DGG
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: 18-bit Bus-interface D-type Latches With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN74ABT16843DGG datasheet File size : 214 kB
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Datasheet text preview:
SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS223E OCTOBER 1992 REVISED MAY 1997
D D D D D D D
Members of the Texas Instruments WidebusTM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Impedance State During Power Up and Power Down High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16843 . . . WD PACKAGE SN74ABT16843 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1LE 1PRE 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2PRE 2LE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
1
SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS223E OCTOBER 1992 REVISED MAY 1997
description (continued)
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16843 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16843 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 9-bit latch) INPUTS PRE L H H H H X CLR X L H H H X OE L L L L L H LE X X H H L X D X X L H X X OUTPUT Q H L L H Q0 Z
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS223E OCTOBER 1992 REVISED MAY 1997
logic diagram (positive logic)
1OE 2
1PRE
55
1CLR
1
1LE
56 S2
1D1
54
C1 1D R
3 1Q1
To Eight Other Channels 27
2OE
2PRE
30
28 2CLR 29 2LE S2 2D1 42 C1 1D R 15 2Q1
To Eight Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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