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Part: SN74ABT16853
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: Dual 8-bit to 9-bit Parity Bus Transceiver
Company: Texas Instruments, Inc.
Datasheet: Download SN74ABT16853 datasheet File size : 214 kB
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Datasheet text preview:
SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B OCTOBER 1992 REVISED JANUARY 1997
D D D D D D D D D D
Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL) Parity-Error Flag With Parity Generator/Checker Latch for Storage of the Parity-Error Flag Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16853 . . . WD PACKAGE SN74ABT16853 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT16853 dual 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus, with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT16853 provide true data at the outputs.
1OEB 1LE 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR 2LE 2OEB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEA 1CLR 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2CLR 2OEA
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1997, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B OCTOBER 1992 REVISED JANUARY 1997
description (continued)
The SN54ABT16853 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16853 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEB L H H X OEA H L L X CLR X X H L H H H L X X L L X LE X L H H H H L L X AI OF H Odd Even NA NA X X X L Odd H Even Odd Even NA = not applicable, NC = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. NA NA A H L X Z Z Z BI OF H NA Odd Even X X A NA B X X OUTPUT AND I/O B A NA NA NA PARITY L H NA NA NA ERR NA H L NC H NC H H L NA A data to B bus and generate inverted parity Isolation§ (parity check) FUNCTION
A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error-flag register
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B OCTOBER 1992 REVISED JANUARY 1997
logic diagram (each transceiver) (positive logic)
A1A8 8 8x 8 EN 8x EN 8 B1B8
OEB
OEA
8 8 MUX
PARITY
1 1 1 1 G1 LE CLR
9
2k P
ERR
ERROR-FLAG FUNCTION TABLE INPUTS CLR L LE L INTERNAL TO DEVICE POINT P L H L H L H L H H X H X X OUTPUT ERRn1 X X L H X L H OUTPUT ERR L H L L H H L H Clear Store Sample FUNCTION
Pass
State of ERR before changes at CLR, LE, or point P
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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