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Details, datasheet, quote on part number:SN74ABT273PWR
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Datasheet text preview:
SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SCBS185B FEBRUARY 1991 REVISED JANUARY 1997
D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package
SN54ABT273 . . . J OR W PACKAGE SN74ABT273 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
description
The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.
SN54ABT273 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLR VCC 2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
The SN54ABT273 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT273 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X H or L D X H L X OUTPUT Q L H L Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
4Q GND CLK 5Q 5D
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SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SCBS185B FEBRUARY 1991 REVISED JANUARY 1997
logic symbol
CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 4 7 8 13 14 17 18 R C1 1D 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D CLK 11 3 CLK(I) 1D C1 R CLR 1 R 2 1Q 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SCBS185B FEBRUARY 1991 REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT273 MIN VCC VIH VIL VI IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate 55 0 4.5 2 0.8 VCC 24 48 10 125 40 0 MAX 5.5 SN74ABT273 MIN 4.5 2 0.8 VCC 32 64 10 85 MAX 5.5 UNIT V V V V mA mA ns/V °C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II Ioff ICEX IO ICC ICC¶ VCC = 4 5 V 4.5 TEST CONDITIONS CONDITIONS II = 18 mA IOH = 3 mA IOH = 3 mA IOH = 24 mA IOH = 32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VI = VCC or GND VI or VO 4.5 V VO = 5.5 V VO = 2.5 V Outputs high 50 Outputs high Outputs low 100 1 24 ±1 ±100 50 200§ 400§ 30 1.5 50 50 200§ 400§ 30 1.5 50 ±1 ±1 ±100 50 200§ 400§ 30 1.5 MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25°C TYP MAX 1.2 2.5 3 2 2 V mV µA µA µA mA µA mA mA pF SN54ABT273 MIN MAX 1.2 2.5 3 V SN74ABT273 MIN MAX 1.2 UNIT V
VOH
VCC = 5.5 V, IO = 0, , , VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND
Ci VI = 2.5 V or 0.5 V 7 * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This data sheet limit may vary among suppliers. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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