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Details, datasheet, quote on part number:SN74ABT32316
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Datasheet text preview:
SN54ABT32316, SN74ABT32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179A JUNE 1992 REVISED JULY 1994
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Members of the Texas Instruments Widebus + TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation UBE TM (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
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Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs ( 32-mA IOH, 64-mA IOL ) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in 80-Pin Plastic Thin Quad Flat (PN) Package With 12 × 12-mm Body Using 0.5-mm Lead Pitch
SN74ABT32316 . . . PN PACKAGE (TOP VIEW)
A1 SELA OEA OEC SELC LEC CLKC CLKENC NC VCC GND C16 C15 C14 C13 C12 GND A2 A3 A4 GND A5 A6 A7 A8 A9 VCC GND A10 A11 A12 A13 A14 GND A15 A16 NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
C11 C10 C9 C8 C7 C6 GND C5 C4 C3 C2 C1 VCC GND B16 B15 B14 B13 B12 GND B11 B10 B9
Copyright © 1994, Texas Instruments Incorporated
NC No internal connection
Widebus+, EPIC-B, and UBE are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
CLKENA CLKA LEA OEB SELB LEB CLKB CLKENB NC V CC GND B1 B2 B3 B4 B5 GND B6 B7 B8
· DALLAS, TEXAS 75265
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SN54ABT32316, SN74ABT32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179A JUNE 1992 REVISED JULY 1994
description
The ABT32316 consists of three 16-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports. Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held at a high or low logic level. If LEA and clock-enable A (CLKENA) are low, data is stored on the low-to-high transition of CLKA. Output data selection is accomplished by the select-control pins. All three ports have active-low output enables, so when the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABT32316 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT32316 is characterized for operation from 40°C to 85°C.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT32316, SN74ABT32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179A JUNE 1992 REVISED JULY 1994
Function Tables
STORAGE INPUTS CLKENA H L L X X X X CLKA X H L X X LEA L L L L L H H A X L H X X L H OUTPUT Q0 L H Q0 Q0 L H
A-port register shown. B and C ports are similar but use CLKENB, CLKENC, CLKB, CLKC, LEB, and LEC. Output level before the indicated steady-state input conditions were established. A-PORT OUTPUT INPUTS OEA H L L SELA X H L OUTPUT A Z Output of C register Output of B register
B-PORT OUTPUT INPUTS OEB H L L SELB X H L OUTPUT B Z Output of A register Output of C register
C-PORT OUTPUT INPUTS OEC H L L SELC X H L OUTPUT C Z Output of B register Output of A register
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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