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Details, datasheet, quote on part number:SN74ABT32501
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Datasheet text preview:
SN54ABT32501, SN74ABT32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS229B JUNE 1992 REVISED NOVEMBER 1994
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Members of the Texas Instruments Widebus + TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ESD Protection Exceeds 2000 V per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA per JEDEC Standard JESD-17
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Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs ( 32-mA IOH, 64-mA IOL ) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch
ABT32501 . . . PZ PACKAGE (TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
2A10 2A9 GND 2A8 2A7 2A6 2A5 GND 2A4 2A3 2A2 2A1 VCC 1A1 1A2 1A3 1A4 GND 1A5 1A6 1A7 1A8 GND 1A9 1A10
2A11 2A12 2A13 GND 2A14 2A15 2A16 2A17 2A18 2OEBA 2LEBA 2CLKBA VCC 2CLKAB 2LEAB 2OEAB 2B18 2B17 2B16 2B15 2B14 GND 2B13 2B12 2B11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2B10 2B9 GND 2B8 2B7 2B6 2B5 GND 2B4 2B3 2B2 2B1 VCC 1B1 1B2 1B3 1B4 GND 1B5 1B6 1B7 1B8 GND 1B9 1B10
Widebus+, EPIC-B, and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
1A11 1A12 1A13 GND 1A14 1A15 1A16 1A17 1A18 1OEBA 1LEBA 1CLKBA VCC 1CLKAB 1LEAB 1OEAB 1B18 1B17 1B16 1B15 1B14 GND 1B13 1B12 1B11
Copyright © 1994, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ABT32501, SN74ABT32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS229B JUNE 1992 REVISED NOVEMBER 1994
description
These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is active low). To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABT32501 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT32501 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEAB L H H H H H LEAB X H H L L L CLKAB X X X H A X L H L H X OUTPUT B Z L H L H B0 B0§
H L L X A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA. Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT32501, SN74ABT32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS229B JUNE 1992 REVISED NOVEMBER 1994
logic diagram (positive logic)
1OEAB 1CLKBA 1LEBA 1OEBA 1CLKAB 1LEAB 1A1 41 37 36 35 39 40 14
CLK LE D CLK LE D 62 1B1
To 17 Other Channels 85 89 90 91 87 86 12
2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB 2A1
CLK LE D CLK LE D 64 2B1
To 17 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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