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Details, datasheet, quote on part number:SN74ABT32543PZ
 
 
Part:SN74ABT32543PZ
Category:Logic => Transceivers => Registered Transceivers
Description:ti SN74ABT32543, 36-Bit Registered Bus Transceivers With 3-State Outputs
Company:Texas Instruments, Inc.
Datasheet:Download SN74ABT32543PZ datasheet   File size : 150 kB
Request For quote:  Find where to buy SN74ABT32543PZ
 



Datasheet text preview:
SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230B ­ JUNE 1992 ­ REVISED JULY 1994
· · · ·
Members of the Texas Instruments Widebus + TM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
· · · ·
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (­ 32-mA IOH, 64-mA IOL ) Bus-Hold Inputs Eliminate the Need for External Pullup Resistors Packaged in 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch
SN74ABT32543 . . . PZ PACKAGE (TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1A9 1A10 GND 1A11 1A12 1A13 1A14 GND 1A15 1A16 1A17 1A18 VCC 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 2A8 GND 2A9 2A10
1A8 1A7 1A6 GND 1A5 1A4 1A3 1A2 1A1 1CEBA 1OEBA 1LEBA VCC 1LEAB 1OEAB 1CEAB 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1B9 1B10 GND 1B11 1B12 1B13 1B14 GND 1B15 1B16 1B17 1B18 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 2B8 GND 2B9 2B10
description
The ABT32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
Widebus+ and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
2A11 2A12 2A13 GND 2A14 2A15 2A16 2A17 2A18 2CEBA 2OEBA 2LEBA VCC 2LEAB 2OEAB 2CEAB 2B18 2B17 2B16 2B15 2B14 GND 2B13 2B12 2B11
Copyright © 1994, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
5­1
SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230B ­ JUNE 1992 ­ REVISED JULY 1994
description (continued)
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABT32543 is characterized for operation over the full military temperature range of ­ 55°C to 125°C. The SN74ABT32543 is characterized for operation from ­ 40°C to 85°C.
FUNCTION TABLE (each 18-bit section) INPUTS CEAB H X L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 L
H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS230B ­ JUNE 1992 ­ REVISED JULY 1994
logic diagram (positive logic)
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 90 91 89 86 85 87 92 C1 1D 84 1B1
C1 1D
To 17 Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 36 35 37 40 41 39 14 C1 1D 62 2B1
C1 1D
To 17 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5­3