|
Details, datasheet, quote on part number:SN74ABT543APWR
| |
Datasheet text preview:
SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS157F JANUARY 1991 REVISED MAY 1997
D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT543A . . . JT OR W PACKAGE SN74ABT543A . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW)
LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB
description
The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT543A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT543A is characterized for operation from 40°C to 85°C.
SN54ABT543A . . . FK PACKAGE (TOP VIEW)
A1 OEBA LEBA NC VCC
4
A2 A3 A4 NC A5 A6 A7
5 6 7 8 9 10
3 2 1 28 27 26 25 24 23 22 21 20
CEBA B1 B2 B3 B4 NC B5 B6 B7
19 11 12 13 14 15 16 17 18
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A8 CEAB GND NC OEAB LEAB B8
Copyright © 1997, Texas Instruments Incorporated
1
SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS157F JANUARY 1991 REVISED MAY 1997
FUNCTION TABLE INPUTS CEAB H X L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 L
H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
logic symbol§
OEBA CEBA LEBA OEAB 11 CEAB 14 LEAB A1 3 3 4 5 6 7 8 9 10 6D 2 23 1 13 1EN3 G1 1C5 2EN4 G2 2C6 1 1 5D 4 22 B1
A2 A3 A4 A5 A6 A7 A8
21 20 19 18 17 16 15
B2 B3 B4 B5 B6 B7 B8
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS157F JANUARY 1991 REVISED MAY 1997
logic diagram (positive logic)
OEBA CEBA LEBA OEAB CEAB LEAB 2 23 1 13 11 14 C1 1D 22 B1
A1
3
C1 1D
To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
