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Details, datasheet, quote on part number:SN74ABT833
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Datasheet text preview:
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C FEBRUARY 1991 REVISED JANUARY 1997
D D D D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (32-mA IOH, 64-mA IOL ) Parity Error Flag With Parity Generator/Checker Register for Storage of the Parity Error Flag Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT833 . . . JT PACKAGE SN74ABT833 . . . DW OR NT PACKAGE (TOP VIEW)
OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK
SN54ABT833 . . . FK PACKAGE (TOP VIEW)
description
The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT833 provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
A3 A4 A5 NC A6 A7 A8
5 6 7 8 9
4
3 2 1 28 27 26 25 24 23 22 21 20
OEA NC V CC B1 B2 B3 B4 B5 NC B6 B7 B8
10
11 19 12 13 14 15 16 17 18
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
ERR CLR GND NC CLK OEB PARITY
Copyright © 1997, Texas Instruments Incorporated
A2 A1
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SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C FEBRUARY 1991 REVISED JANUARY 1997
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT833 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT833 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEB L H X OEA H L X CLR X H L H H H L H H L L X CLK X X No No X Ai OF H's Odd Even NA X X X Odd Even Odd Even NA NA A H L X Z Z Z Bi OF H's NA Odd Even X A NA B X OUTPUT AND I/O B A NA NA PARITY L H NA NA ERR NA H L H NC H H L NA A data to B bus and generate inverted parity Isolation§ FUNCTION A data to B bus and generate parity B data to A bus and check parity Check error-flag register
NA = not applicable, NC = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus.
logic symbol¶
CLK CLR OEA OEB A1 A2 A3 A4 A5 A6 A7 A8 13 11 1 14 2 3 4 5 6 7 8 9 8 8
A Bus B Bus
CLK CLR OEA OEB 1
ERR 10 ERR
PARITY 1
15 23 22 21 20 19 18 17 16
PARITY B1 B2 B3 B4 B5 B6 B7 B8
¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C FEBRUARY 1991 REVISED JANUARY 1997
logic diagram (positive logic)
A1A8 29 8 EN 8x 8 EN OEB 14 8x 8 1623 B1B8
15 OEA 1 8
PARITY
8 1 MUX 1 1 1 G1 1D CLK CLR 13 11 R C1 10 ERR 9 2k
P
Pin numbers shown are for the DW, JT, and NT packages. ERROR-FLAG FUNCTION TABLE INPUTS CLR H H H CLK INTERNAL TO DEVICE POINT P H X L OUTPUT PRE-STATE ERRn1 H L X OUTPUT ERR H L L Sample FUNCTION
L X X X H Clear The state of ERR before any changes at CLR, CLK, or point P
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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