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Details, datasheet, quote on part number:SN74AC573PWLE
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Datasheet text preview:
SN54AC573, SN74AC573 OCTAL D TYPE TRANSPARENT LATCHES WITH 3 STATE OUTPUTS
SCAS542D - OCTOBER 1995 - REVISED OCTOBER 2003
D D D D
2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V 3-State Outputs Drive Bus Lines Directly
SN54AC573 . . . J OR W PACKAGE SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D Inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85 C 85°C SOP - NS SSOP - DB TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tube Tube Tube
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
SN54AC573 . . . FK PACKAGE (TOP VIEW)
2D 1D OE VCC
3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q 2Q 3Q 4Q 5Q 6Q
ORDERABLE PART NUMBER SN74AC573N SN74AC573DW SN74AC573DWR SN74AC573NSR SN74AC573DBR SN74AC573PW SN74AC573PWR SNJ54AC573J SNJ54AC573W SNJ54AC573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2003, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
8D GND LE 8Q 7Q
TOP-SIDE MARKING SN74AC573N AC573 AC573 AC573 AC573 SNJ54AC573J SNJ54AC573W SNJ54AC573FK
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SCAS542D - OCTOBER 1995 - REVISED OCTOBER 2003
SN54AC573, SN74AC573 OCTAL D TYPE TRANSPARENT LATCHES WITH 3 STATE OUTPUTS
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE LE 1 11
C1 1D 2 1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AC573, SN74AC573 OCTAL D TYPE TRANSPARENT LATCHES WITH 3 STATE OUTPUTS
SCAS542D - OCTOBER 1995 - REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC573 MIN VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL t/v Low-level output current Input transition rise or fall rate VCC = 4.5 V VCC = 5.5 V VCC = 4.5 V VCC = 5.5 V 0 0 2 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC -12 -24 -24 12 24 24 8 0 0 MAX 6 SN74AC573 MIN 2 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC -12 -24 -24 12 24 24 8 ns/V mA mA V V V V MAX 6 UNIT V
High-level input voltage
High-level output current
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 3V IOH = -50 µA VOH IOH = -12 mA IOH = -24 mA IOH = -75 mA IOL = 50 µA VOL IOL = 12 mA IOL = 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ±0.1 ±0.25 4 0.1 0.1 0.1 0.36 0.36 0.36 MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25°C TYP MAX SN54AC573 MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 ±5 80 MAX SN74AC573 MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 ±2.5 40 µA µA µA pF V V MAX UNIT
II IOZ ICC Ci
VI = VCC or GND 5V 5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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