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Details, datasheet, quote on part number:SN74ACT2440FN
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Datasheet text preview:
SN74ACT2440 NuBusTM INTERFACE CONTROLLER
SCHS010 D3158, OCTOBER 1988 REVISED JANUARY 1991
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Designed for NuBusTM Interface Applications Supports Master, Slave, and Master/Slave Applications Conforms to ANSI/IEEE Std 1196-1987 Designed to Operate With SN74BCT2420 NuBusTM Data/Address Interface Devices Supports NuBusTM 1987 Block Transfers With the Addition of the SN74ALS2442 EPICTM (Enhanced Performance Implanted CMOS) 1-µm Process Fully TTL-Compatible Dependable Texas Instruments Quality and Reliability
FN PACKAGE (TOP VIEW) GND TM1 TM0 SPV IDEQ AEN ACLK DEN DCLK VCC GND A/ D ADEN BT 3 BT 2 BT 1 BT 0 RESET ARB0 GND ARB1 GND ARB2 GND ARB3 GND VCC START ACK GND RQST GND NMRQ CLK
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
description
A1 A0 VCC SIACK SGNTA LOCTM1 LOCTM0 NMREQ GND MHOLD LACK MLREQ MRDY NREQ MDONE NLOCK NMSTR
The SN74ACT2440 NuBusTM Controller handles NuBusTM signaling protocol in compliance with ANSI/IEEE Std 1196-1987. The device allows a simple connection to the NuBusTM; typical configurations include master-only, slave-only, and master/slave. Additionally, it provides extra status and control lines to facilitate more sophisticated approaches. With the addition of the SN74ALS2442, slave block transfers can be supported by this device. For additional details on block transfers, consult the SN74ALS2442 data sheet and the application note titled Supporting NuBusTM Block Slave Transfers Using Texas Instruments SN74ACT2440, SN74BCT2420, and SN74ALS2442. Figure 1 shows a typical NuBusTM interface using the 'ACT2440. Data and address buffering is handled via two SN74BCT2420s. The SN74BCT2420s are BiCMOS buffers designed specifically for supporting NuBusTM interfacing. The 'ACT2440 provides the buffer control signals needed to directly drive the SN74BCT2420s; however, in simpler applications, standard SSI and MSI buffers may be used in place of the 'BCT2420s. The 'ACT2440 is comprised of five major signal groups: byte decode signals, data/address interface-control signals, master/slave input signals, NuBusTM card-slot signals, and NuBusTM status signals. Byte decode determines which type of NuBusTM cycle is being performed. Data/address interface control provides the buffering signals required to multiplex and de-multiplex the NuBusTM data/address lines. The master/slave inputs control the master- and slave-state machines. The NuBusTM card-slot signals interface with the NuBusTM. The NuBusTM status signals indicate the status of the master/slave-state machines and provide buffered NuBusTM signals. Refer to Table 1 for additional details. The SN74ACT2440 is characterized for operation from 0°C to 70°C.
ID3 ID2 ID1 ID0 NSTART NACK NLRST GND NTM1 NTM0 NLTM1 NLTM0 NCLK NCLK SEREQ VCC GND
NuBus is a trademark of Texas Instruments Incorporated. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1991, Texas Instruments Incorporated
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SN74ACT2440 NuBusTM INTERFACE CONTROLLER
SCHS010 D3158, OCTOBER 1988 REVISED JANUARY 1991
Data/Address Interface SN74BCT2420 BOARD SPECIFIC FUNCTION A31A0 2 D31D0 32 16 IDEQ 32 16 A15 -A0 AEN ACLK D15 -D0 DEN NuBusTM Controller ACT2440 AOA1 BT0 BT1 BT2 BT3 DCLK ALE DLE A/D Data/Address Interface SN74BCT2420 IDEQ 16 AEN ACLK 16 M A S T E R S L A V E NREQ MRDY MLREQ LACK MHOLD NMREQ LOCTM0 LOCTM1 SGNTA SIACK NMSTR NSTART NACK NLOCK NLTMO NLTM1 NCLK NCLK NLRST MDONE NTMO NTM1 SEREQ DEN DCLK IDEQ A15 -A0 AEN ACLK D15 -D0 DEN DCLK ALE DLE 16 A/D ADEN 4 4 A/D 32 ADEN ADEN 16 ID3 -ID0
NuBusTM Card-Slot Signals
PFW SP
B Y T E
D E C O D E
I N P U T S
AD31AD0
ID3 -0 ARB0 -3 CLK NMRQ RESET START RQST ACK TM0 TM1 SPV
ID3 -0 ARB0 -3 CLK NMRQ RESET START RQST ACK TM0 TM1 SPV
N u B u s S T A T U S
2
Figure 1. Typical 'ACT2440 NuBusTM Interface
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SN74ACT2440 NuBusTM INTERFACE CONTROLLER
SCHS010 D3158, OCTOBER 1988 REVISED JANUARY 1991
Terminal Functions
As previously explained, the input and output signals on the 'ACT2440 can be functionally organized into five groups. The following tables briefly describe the controller signals in each group.
DATA/ADDRESS INTERFACE CONTROL SIGNALS PIN NAME ACLK A/D NO. 3 66 DESCRIPTION Address clock. This output loads NuBusTM address information onto the local board. During both master and slave start cycles, this output changes on the sample edge (high-to-low) of the NuBusTM clock signal (CLK). Output select. This normally high output controls the multiplexing function of the address and data information onto theNuBusTM. When low, address information is indicated. When high, data information is indicated. When the local boardis the NuBus master, A/D goes low on the driving edge (low-to-high) of start and remains low for one NuBusTM clock period. Output enable. This active-low output enables data or address information onto the NuBusTM. ADEN is asserted on the driving edge (low-to-highof the NuBusTM clock signal (CLK) under any of the following conditions: The local board is the NuBusTM master performing a write cycle and continuing until an acknowledge (ACK) is received from the NuBusTM. The local board is the NuBusTM master performing a read cycle and continuing for one NuBusTM clock cycle. The local board is the selected NuBusTM slave during an acknowledge cycle and the current cycle is a read. Address enable. This active-low output signal enables address information onto the local board. When selected as a NuBusTM slave, AEN goes low on the first sample edge after slave grant access (SGNTA) is asserted. AEN returns inactive on the first sample edge after (SGNTA) returns inactive. If SGNTA is active (low) before the first sample edge after START, then address information is placed onto the local board on the first sample edge after START. Data clock. This output loads NuBusTM data onto the local board. This output changes on the sample edge (high-to-low) of the NuBusTM clock signal (CLK) under any of the following sets of comditions: The local board is the NuBusTM master, the current cycle is a read, and an acknowledge (ACK) or interim acknowledge (TM0 during block transfers) has been received. The local board is a NuBusTM slave, the current cycle is a write, and slave grant access (SGNTA) is asserted. The local board is a NuBusTM slave, the current cycle is a block write. The first rising edge of DCLK will occur on the first sample edge after SGNTA is taken active (low) and will remain high for two clock cycles. If SGNTA is active (low) during the start cycle, DCLK will go active (high) on the first sample edge after START. The SIACK iinput controls the remaining DCLK cycles with the exception of the last DCLK cycle. When the SIACK input is taken active (low), DCLK will go active on the following sample edge. DCLK will remain high for one clock cycle and return low, regardless of the SIACK input. The final DCLK cycle is controlled by the Local Acknowledge Input (LACK), as on normal write cycles. Data Enable. The active-low output enables data to be placed onto the local board. DEN is asserted under either of the following conditions: The local board is the NuBusTM master performing a read cycle. (DEN goes low on the sample edge (high-to-low) of the acknowledge cycle and remains low until the first sample edge after MHOLD returns inactive.) The local board is the selected NuBusTM slave performing a write cycle. (DEN goes low on the first sample edge after slave grant access (SGNTA) is asserted and remains low until the first sample edge after SGNTA returns inactive.)
ADEN
65
AEN
4
DCLK
1
DEN
2
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