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Part: SN74ACT7805-40DLR
Category:
Logic
-> FIFOs
-> Synchronous FIFOs
Description: ti SN74ACT7805, 256 X 18 Synchronous Fifo Memory
Company: Texas Instruments, Inc.
Datasheet: Download SN74ACT7805-40DLR datasheet File size : 214 kB
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Datasheet text preview:
SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201B MARCH 1991 REVISED APRIL 1998
D D D D D D D D D D D D D
Member of the Texas Instruments WidebusTM Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 256 Words by 18 Bits Low-Power Advanced CMOS Technology Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag Bidirectional Configuration and Width Expansion Without Additional Logic Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 67 MHz Pin-to-Pin Compatible With SN74ACT7803 and SN74ACT7813 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
DL PACKAGE (TOP VIEW)
description
28 29 The SN74ACT7805 is a 256-word × 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.
RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE WRTCLK WRTEN2 WRTEN1 IR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
OE1 Q17 Q16 Q15 GND Q14 VC C Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VC C Q4 Q3 Q2 GND Q1 Q0 RDCLK RDEN OE2 OR
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and OEC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201B MARCH 1991 REVISED APRIL 1998
logic symbol
FIFO 256 × 18 SN74ACT7805
1 RESET WRTCLK WRTEN1 WRTEN2 RDCLK OE1 OE2 32 56 30 25 27 26
RESET
WRTCLK & WRTEN IN RDY RDCLK & EN1 HALF-FULL ALMOST FULL/EMPTY OUT RDY & RDEN 28 22 24 29 IR HF AF/AE OR
31 RDEN PEN 23 PROGRAM ENABLE 33 34 36 37 38 40 41 42 43 Data Data 1 45 46 47 48 49 51 53 54 17 17 55
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
21 20 19 18 17 16 15 14 12 11 9 8 7 6 5 4 3 2
0
0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201B MARCH 1991 REVISED APRIL 1998
functional block diagram
OE1 OE2 Output Control
D0D17
Location 1 RDCLK RDEN Synchronous Read Control Read Pointer Location 2
256 × 18 RAM WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer
Location 255 Location 256
Register
Q0Q17
RESET PEN
Reset Logic
StatusFlag Logic
OR IR HF AF/AE
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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