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Part: SN74ACT7806-40DL
Category:
Logic
-> FIFOs
-> Asynchronous FIFOs
Description: ti SN74ACT7806, 256 X 18 Asynchronous Fifo Memory
Company: Texas Instruments, Inc.
Datasheet: Download SN74ACT7806-40DL datasheet File size : 214 kB
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Datasheet text preview:
SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438C APRIL 1992 REVISED APRIL 1998
D D D D D D D D D D D
Member of the Texas Instruments WidebusTM Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 Words by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-Empty Flag Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 50 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
DL PACKAGE (TOP VIEW)
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.
RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE LDCK NC NC FULL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OE Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 UNCK NC NC EMPTY
NC No internal connection
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 Y) words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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1
SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438C APRIL 1992 REVISED APRIL 1998
description (continued)
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is high. The SN74ACT7806 is characterized for operation from 0°C to 70°C.
logic symbol
FIFO 256 × 18 SN74ACT7806 RESET LDCK UNCK OE PEN 23 1 25 32 56 RESET LDCK UNCK EN1 PROGRAM ENABLE 33 34 36 37 38 40 41 42 43 Data Data 1 45 46 47 48 49 51 53 54 17 17 55 FULL HALF-FULL ALMOST FULL/EMPTY EMPTY 28 22 24 29 EMPTY FULL HF AF/AE
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
21 20 19 18 17 16 15 14 12 11 9 8 7 6 5 4 3 2
0
0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
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SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438C APRIL 1992 REVISED APRIL 1998
functional block diagram
OE D0D17
Location 1 UNCK Read Pointer Location 2
256 × 18 SRAM Write Pointer
LDCK
Location 255 Location 256
Q0 Q17
EMPTY RESET PEN Reset Logic StatusFlag Logic FULL HF AF/AE
Terminal Functions
TERMINAL NAME AF/AE NO. 24 29, 1112, 1214 29 28 22 25 56 23 3334, 3638, 4043, 4549, 51, 5355 1 32 I/O DESCRIPTION Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (256 Y) or more words. AF/AE is high after reset. 18-bit data input port Empty flag. EMPTY is high when the FIFO memory is not empty; EMPTY is low when the FIFO memory is empty or upon assertion of RESET. Full flag. FULL is high when the FIFO memory is not full or upon assertion of RESET; FULL is low when the FIFO memory is full. Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset. Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high. Output enable. When OE is high, the data outputs are in the high-impedance state. Program enable. After reset and before the first word is written to the FIFO, the binary value on D0D6 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. 18-bit data output port Reset. A low level on this input resets the FIFO and drives FULL high and HF and EMPTY low. Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
O
D0D17 EMPTY FULL HF LDCK OE PEN
I O O O I I I
Q0Q17 RESET UNCK
O I I
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