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Part: SN74ACT7807-20
Category:
Logic
-> Memory Interface
-> CMOS/BiCMOS->AC/ACT Family
Description: Clocked Fifo: 2kx9
Company: Texas Instruments, Inc.
Datasheet: Download SN74ACT7807-20 datasheet File size : 214 kB
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Datasheet text preview:
SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D JANUARY 1991 REVISED APRIL 1998
D D D D D D D
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 2048 Words by 9 Bits Low-Power Advanced CMOS Technology Programmable Almost-Full/Almost-Empty Flag
D D D D D D
Input-Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 12 ns With a 50-pF Load Data Rates up to 67 MHz 3-State Outputs Package Options Include 44-Pin Plastic Leaded Chip Carrier (FN) and 64-Pin Thin Quad Flat (PAG, PM) Packages
description
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D JANUARY 1991 REVISED APRIL 1998
FN PACKAGE (TOP VIEW)
D0 D1 D2 GND D3 D4 D5 VCC D6 D7 D8
VCC HF AF/AE GND PEN RESET VCC NC OE GND Q0
65 7 8 9 10 11 12 13 14 15 16 43 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 17 18 19 20 21 22 23 24 25 26 27 28
Q1 VC C Q2 Q3 GND Q4 VC C Q5 Q6 GND Q7
Q2 Q3 GND
GND Q4 VCC VCC
Q1 VCC VCC
Q5 Q6 GND GND
GND WRTCLK WRTEN1/DP9 WRTEN2 IR OR RDEN2 RDEN1 RDCLK VCC
PAG OR PM PACKAGE (TOP VIEW)
Q8 Q7 NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC Q0 GND GND OE NC VCC VCC RESET PEN GND GND AF/AE HF VCC VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC Q8 VC C VC C RDCLK RDEN1 NC RDEN2 OR IR WRTEN2 WRTEN1/DP9 WRTCLK GND GND NC
NC No internal connection
2
NC D0 D1 D2 GND GND D3 D4 NC D5 VCC VCC D6 D7 D8 NC
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SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D JANUARY 1991 REVISED APRIL 1998
logic symbol
FIFO 2048 × 9 SN74ACT7807 RESET WRTCLK & WRTEN RDCLK EN1 & RDEN RDEN2 PEN 24 2 PROGRAM ENABLE 40 39 37 36 Data Data 1 34 32 31 29 8 8 28 IN RDY HALF FULL 26 42 25 ALMOST FULL/EMPTY OUT RDY 22 5 4 23 IR HF AF/AE OR
RESET WRTCLK WRTEN1/DP9 WRTEN2 RDCLK OE RDEN1
1 19 20 21
D0 D1 D2 D3 D4 D5 D6 D7 D8
7 8 9 11 12 13 15 16 17
0
0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package.
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3
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