|
Details, datasheet, quote on part number:SN74AHC08MPWREP
| |
Datasheet text preview:
SN74AHC08-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS484 JUNE 2003
D D D D D D D D D
Controlled Baseline One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of 55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree Operating Range 2-V to 5.5-V VCC EPIC (Enhanced-Performance Implanted CMOS) Process Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE (TOP VIEW)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
description/ordering information
This Y
+ A · B or Y + A ) B in positive logic.
TA 55°C to 125°C to 125°C SOIC D TSSOP PW
device
is
a
quadruple
2-input
positive-AND
gate
that
performs
the
Boolean
function
ORDERING INFORMATION
PACKAGE Tape and reel Tape and reel ORDERABLE PART NUMBER SN74AHC08MDREP SN74AHC08MPWREP TOP-SIDE MARKING AHC08MEP AHC08EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y H L L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74AHC08-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS484 JUNE 2003
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 & 3 1Y
2Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A B Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AHC08-EP QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS484 JUNE 2003
recommended operating conditions (see Note 3)
MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VCC = 3 V VCC = 5.5 V VI VO IOH Input voltage Output voltage High-level output current VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 0 0 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC 50 4 8 50 4 8 100 20 V V V V MAX 5.5 UNIT V
VIL
Low-level input voltage
mA
mA
mA
mA ns/V
IOL
Low-level output current
t/v
Input transition rise or fall rate transition rise or fall rate
TA Operating free-air temperature 55 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS VCC 2V IOH = 50 mA VOH IOH = 4 mA IOH = 8 mA IOL = 50 mA VOL IOL = 4 mA II ICC Ci A or B inputs IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VI = VCC or GND IO = 0 3V 4.5 V 3V 4.5 V 2V 3V 4.5 V 3V 4.5 V 0 V to 5.5 V 5.5 V 5V 4 MIN 1.9 2.9 4.4 2.58 3.94 0.1 0.1 0.1 0.36 0.36 ±0.1 2 10 TA = 25°C TYP MAX 2 3 4.5 MIN 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.5 0.5 ±1 20 V V MAX UNIT
mA mA
pF
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
