|
Details, datasheet, quote on part number:SN74AHC174PW
| |
Datasheet text preview:
SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
SCLS425E JUNE 1998 REVISED JANUARY 2000
D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Contain Six Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54AHC174 . . . J OR W PACKAGE SN74AHC174 . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3D 3Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 6Q 6D 5D 5Q 4D 4Q CLK
SN54AHC174 . . . FK PACKAGE (TOP VIEW)
1D 2D NC 2Q 3D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q CLR NC VCC 6Q 6D 5D NC 5Q 4D
NC No internal connection D X H L X OUTPUT Q L H L Q0
Copyright © 2000, Texas Instruments Incorporated
The 'AHC174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 2-V to 5.5-V VCC operation.
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. The SN54AHC174 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHC174 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3Q GND NC CLK 4Q
description
1
SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
SCLS425E JUNE 1998 REVISED JANUARY 2000
logic symbol
CLR CLK 1D 2D 3D 4D 5D 6D 1 9 3 4 6 11 13 14 R C1 1D 2 5 7 10 12 15 1Q 2Q 3Q 4Q 5Q 6Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram (positive logic)
CLR 1
CLK 1D
9 3
1D C1 R 2 1Q
To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
SCLS425E JUNE 1998 REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC174 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V IOL Low-level output current VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3 V VCC = 5.5 V 0 0 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC 50 4 8 50 4 8 100 20 0 0 MAX 5.5 SN74AHC174 MIN 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC 50 4 8 50 4 8 100 20 V V V V MAX 5.5 UNIT V
mA
mA
mA
mA ns / V
Dt /Dv
Input transition rise or fall rate transition rise or fall rate
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
|
|
