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Details, datasheet, quote on part number:SN74AHCT125
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Datasheet text preview:
SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS264N DECEMBER 1995 REVISED SEPTEMBER 2002
D D
Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17
D
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54AHCT125 . . . FK PACKAGE (TOP VIEW)
1OE
GND
NC No internal connection
description/ordering information
The 'AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE QFN RGY PDIP N SOIC D 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC FK Tape and reel Tube Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74AHCT125RGYR SN74AHCT125N SN74AHCT125D SN74AHCT125DR SN74AHCT125NSR SN74AHCT125DBR SN74AHCT125PWR SN74AHCT125DGVR SNJ54AHCT125J SNJ54AHCT125W SNJ54AHCT125FK AHCT125 HB125 HB125 HB125 SNJ54AHCT125J SNJ54AHCT125W SNJ54AHCT125FK TOP-SIDE MARKING HB125 SN74AHCT125N AHCT125
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
1
14 13 4OE 12 4A 11 4Y 10 3OE 9 3A
VCC
1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13
SN54AHCT125 . . . J OR W PACKAGE SN74AHCT125 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW)
SN74AHCT125 . . . RGY PACKAGE (TOP VIEW)
1A 1Y 2OE 2A 2Y
2 3 4 5 6 7 8
4A NC 4Y NC 3OE
3Y
1
SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS264N DECEMBER 1995 REVISED SEPTEMBER 2002
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
logic diagram (positive logic)
1 1OE 1A 2 3 1Y
2OE 2A
4 5 6
2Y
10 3OE 3A 9 8 3Y
13 4OE 4A 12 11 4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCLS264N DECEMBER 1995 REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54AHCT125 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC 8 8 20 0 0 MAX 5.5 SN74AHCT125 MIN 4.5 2 0.8 5.5 VCC 8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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