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Details, datasheet, quote on part number:SN74AHCT125QPWRQ1
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Datasheet text preview:
SN74AHCT125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCLS508 JUNE 2003
D D D D D
Qualification in Accordance With AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Inputs Are TTL-Voltage Compatible
D OR PW PACKAGE (TOP VIEW)
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
Contact factory for details. Q100 qualification data available on request.
description/ordering information
The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA 40°C to 125°C SOIC D PACKAGE Tape and reel ORDERABLE PART NUMBER SN74AHCT125QDRQ1 TOP-SIDE MARKING AHCT125Q
TSSOP PW Tape and reel SN74AHCT125QPWRQ1 HB125Q Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74AHCT125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCLS508 JUNE 2003
logic diagram (positive logic)
1 1OE 1A 2 3 1Y
2OE 2A
4 5 6
2Y
10 3OE 3A 9 8 3Y
13 4OE 4A 12 11 4Y
Pin numbers shown are for the D and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AHCT125-Q1 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCLS508 JUNE 2003
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC 8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci Co IOH = 50 mA IOH = 8 mA IOL = 50 mA IOL = 8 mA VI = 5.5 V or GND VO = VCC or GND VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND IO = 0 TEST CONDITIONS VCC 4.5 V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 5.5 V 5V 5V 4 15 TA = 25°C MIN TYP MAX 4.4 3.94 0.1 0.36 ±0.1 ±0.25 2 1.35 10 4.5 MIN 4.4 3.8 0.1 0.44 ±1 ±2.5 20 1.5 10 MAX UNIT V V
mA mA mA
mA pF pF
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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