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Details, datasheet, quote on part number:SN74AHCT573DW
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Datasheet text preview:
SN54AHCT573, SN74AHCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
D D D
Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54AHCT573 . . . J OR W PACKAGE SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
The 'AHCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
SN54AHCT573 . . . FK PACKAGE (TOP VIEW)
2D 1D OE VCC
3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q 2Q 3Q 4Q 5Q 6Q
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION
TA PDIP N SOIC DW DW 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW PW TVSOP DGV CDIP J 55°C to 125°C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74AHCT573N SN74AHCT573DW SN74AHCT573DWR SN74AHCT573NSR SN74AHCT573DBR SN74AHCT573PW SN74AHCT573PWR SN74AHCT573DGVR SNJ54AHCT573J SNJ54AHCT573W SNJ54AHCT573FK TOP-SIDE MARKING SN74AHCT573N AHCT573 AHCT573 HB573 HB573 HB573 SNJ54AHCT573J SNJ54AHCT573W SNJ54AHCT573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
8D GND LE 8Q 7Q
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SN54AHCT573, SN74AHCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE 1
LE
11 C1 19
1D
2
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AHCT573, SN74AHCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54AHCT573 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC 8 8 20 0 0 MAX 5.5 SN74AHCT573 MIN 4.5 2 0.8 5.5 VCC 8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci TEST CONDITIONS CONDITIONS IOH = 50 mA IOH = 8 mA IOL = 50 mA IOL = 8 mA VI = 5.5 V or GND VO = VCC or GND VI = 5.5 V or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VCC 4.5 V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 5.5 V 5V 2.5 MIN 4.4 3.94 0.1 0.36 ±0.1 ±0.25 4 1.35 10 TA = 25°C TYP MAX 4.5 SN54AHCT573 MIN 4.4 3.8 0.1 0.44 ±1* ±2.5 40 1.5 MAX SN74AHCT573 MIN 4.4 3.8 0.1 0.44 ±1 ±2.5 40 1.5 10 MAX UNIT V V
mA mA mA
mA pF pF
Co 5V 3 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, Vcc = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 5 3.5 1.5 SN54AHCT573 MIN 5 3.5 1.5 MAX SN74AHCT573 MIN 5 3.5 1.5 MAX UNIT ns ns ns
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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