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Details, datasheet, quote on part number:SN74AHCT595DR
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Datasheet text preview:
SN54AHCT595, SN74AHCT595 8 BIT SHIFT REGISTERS WITH 3 STATE OUTPUT REGISTERS
SCLS374K - MAY 1997 - REVISED SEPTEMBER 2003
D D D D D
Inputs Are TTL-Voltage Compatible 8-Bit Serial-In, Parallel-Out Shift Shift Register Has Direct Clear Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
SN54AHCT595 . . . J OR W PACKAGE SN74AHCT595 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
The 'AHCT595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
QB QC QD QE QF QG QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC QA SER OE RCLK SRCLK SRCLR Q H
SN54AHCT595 . . . FK PACKAGE (TOP VIEW)
QC QB NC VCC QA QD QE NC QF QG
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
SER OE NC RCLK SRCLK
QH
GND NC Q H
NC - No internal connection
ORDERING INFORMATION
TA PDIP - N SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74AHCT595N SN74AHCT595D SN74AHCT595DR SN74AHCT595NSR SN74AHCT595DBR SN74AHCT595PW SN74AHCT595PWR SNJ54AHCT595J SNJ54AHCT595W SNJ54AHCT595FK HB595 SNJ54AHCT595J SNJ54AHCT595W SNJ54AHCT595FK AHCT595 AHCT595 HB595 TOP-SIDE MARKING SN74AHCT595N
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2003, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
SRCLR
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SCLS374K - MAY 1997 - REVISED SEPTEMBER 2003
SN54AHCT595, SN74AHCT595 8 BIT SHIFT REGISTERS WITH 3 STATE OUTPUT REGISTERS
FUNCTION TABLE INPUTS SER X X X L H X X X SRCLK X X X X X SRCLR X X L H H H X X RCLK X X X X X X OE H L X X X X X X FUNCTION Outputs QA-QH are disabled. Outputs QA-QH are enabled. Shift register is cleared. First stage of the shift register goes low. Other stages store the data of previous stage, respectively. First stage of the shift register goes high. Other stages store the data of previous stage, respectively. Shift-register state is not changed. Shift-register data is stored in the storage register. Storage-register state is not changed.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AHCT595, SN74AHCT595 8 BIT SHIFT REGISTERS WITH 3 STATE OUTPUT REGISTERS
SCLS374K - MAY 1997 - REVISED SEPTEMBER 2003
logic diagram (positive logic)
OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q
15
QA
2D Q C2 R
3D C3 Q
1
QB
2D Q C2 R
3D C3 Q
2
QC
2D Q C2 R
3D C3 Q
3
QD
2D Q C2 R
3D C3 Q
4
QE
2D Q C2 R
3D C3 Q
5
QF
2D Q C2 R
3D C3 Q
6
QG
2D Q C2 R
3D C3 Q
7
QH Q H
9
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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