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Details, datasheet, quote on part number:SN74ALS114AN
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Datasheet text preview:
SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 D2661, DECEMBER 1982 REVISED MAY 1986
· · · · ·
Fully Buffered to Offer Maximum isolation from External Disturbance Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Typical Maximum Clock Frequency 30 MHz Typical Power Dissipation per Flip-Flop 6 mW Dependable Texas Instruments Quality and Reliability
SN54ALS114A . . . J PACKAGE SN74ALS114A . . . D OR N PACKAGE (TOP VIEW)
CLR 1K 1J 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VC C CLK 2K 2J 2PRE 2Q 2Q
SN54ALS114A . . . FK PACKAGE
description
These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS114A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS114A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS PRE L H L H H H H CLR H L L H H H H CLK X X X J X X X L H L H K X X X L L H H OUTPUTS Q H L H Q0 H L Q L H H Q0 L H 2J 2K 1K 2PRE 1PRE 1J
(TOP VIEW)
1J NC 1PRE NC 1Q
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1K 1CLR NC VCC CLK 2K NC 2J NC 2PRE
NCNo internal connection
logic symbol
CLR CLK 1 13 R C1 4 S 3 1J 2 1K 10 11 12 9 2Q 8 2Q 6 1Q 5 1Q
TOGGLE This symbol is in accordance with ANSI/IEEE Std 911-1984 and IEC Publication 617-12. Pin numbers are for D, J, and N packages.
H H H X X Q0 Q0 The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at Preset and Clear are near VIL maximum. Furthermore, this configuration is nonstable; that is, it will not persist when either Preset or Clear returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1986, Texas Instruments Incorporated 5BASIC
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1Q GND NC 2Q 2Q
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SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 D2661, DECEMBER 1982 REVISED MAY 1986
logic diagram (positive logic)
Q
Q
PRE K
CLR
J
CLK To Other Flip-Flop
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range: SN54ALS114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74ALS114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
recommended operating conditions
SN54ALS114A MIN VCC VIH VIL IOH IOL fclock tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency PRE or CLR low Pulse duration CLK high CLK low tsu th TA Setup time before CLK Hold time, data after CLK Operating free-air temperature Data PRE or CLR inactive 0 20 20 20 25 25 0 55 125 4.5 2 0.7 0.4 4 25 0 10 16.5 16.5 22 20 0 0 70 ns ns °C ns NOM 5 MAX 5.5 SN74ALS114A MIN 4.5 2 0.8 0.4 8 30 NOM 5 MAX 5.5 UNIT V V V mA mA mHz
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 D2661, DECEMBER 1982 REVISED MAY 1986
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL J, K, or CLK PRE or CLR J, K, or CLK PRE or CLR J, K, or CLK PRE or CLR TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, II = 18 mA IOH = 0.4 mA IOL = 4 mA IOL = 8 mA VI = 7 V VI = 2.7 V VI = 0.4 V MIN SN54ALS114A TYP MAX 1.5 VCC 2 0.25 0.4 0.35 0.1 0.2 20 40 0.2 0.4 0.5 0.1 0.2 20 40 0.2 0.4 V mA µA mA VCC 2 MIN SN74ALS114A TYP MAX 1.5 UNIT V V
IO VCC = 5.5 V, VO = 2.25 V 30 112 30 112 mA ICC VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA All typical values are at VCC = 5 V, TA = 25°C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.
switching characteristics (see Note 2)
VCC = 4.5 V to 5.5 V, CL = 50 pF, PARAMETER FROM (INPUT) TO (OUTPUT) RL = 500 , TA = MIN to MAX SN54ALS114A SN74ALS114A MIN fmax tPLH tPHL tPLH 25 PRE or CLR Q or Q Q or Q 3 4 3 5 29 30 28 31 MAX MIN 30 3 4 3 5 15 18 15 19 ns MAX MHz ns UNIT
CLK tPHL NOTE 2: Load circuit and Voltage waveforms are shown in Section 1.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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