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Details, datasheet, quote on part number:SN74ALS233BN
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Datasheet text preview:
SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253B MARCH 1990 REVISED APRIL 1998
D D D D D D
Independent Asychronous Inputs and Outputs 16 Words by 5 Bits Data Rates From up to 40 MHz Fall-Through Time 14 ns Typ 3-State Outputs Package Options Include Plastic Small-Outline Package (DW), Plastic Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N)
DW OR N PACKAGE (TOP VIEW)
description
This 80-bit memory uses advanced low-power Schottky technology and features high speed and a fast fall-through time. It is organized as 16 words by 5 bits. A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40 MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect.
OE FULL1 FULL LDCK D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VC C EMPTY+1 UNCK EMPTY Q0 Q1 Q2 Q3 Q4 RST
FN PACKAGE (TOP VIEW)
FULL FULL1 OE VCC EMPTY+1 LDCK D0 D1 D2 D3
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13
UNCK EMPTY Q0 Q1 Q2
Status of the FIFO memory is monitored by the FULL, EMPTY, FULL1, and EMPTY+1 output flags. The FULL output is low when the memory is full and high when it is not full. The FULL1 output is low when the memory contains 15 data words. The EMPTY output is low when the memory is empty and high when it is not empty. The EMPTY+1 output is low when one word remains in memory. A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets FULL, FULL1, and EMPTY+1 high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS233B is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
D4 GND RST Q4 Q3
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SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253B MARCH 1990 REVISED APRIL 1998
logic symbol
FIFO 16 × 5 (ALS233B) CTR RST LDCK UNCK OE 11 4 18 1 CT = 0 1(+/C2) 3 EN4 16 15 14 13 12 (CT = 16) G1 CT = 15 CT = 1 (CT = 0) G3 3 2 19 17 FULL FULL1 EMPTY+1 EMPTY
D0 D1 D2 D3 D4
5 6 7 8 9
2D
4
Q0 Q1 Q2 Q3 Q4
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253B MARCH 1990 REVISED APRIL 1998
logic diagram (positive logic)
1 OE 1 2 3 4 5 6 7 8 + 9 10 Write 11 Address 12 13 14 CT = 1 15 16 1 2 3 4 5 6 7 8 + 9 10 Read 11 12 Address 13 14 CT = 1 15 16 Ring Counter CTR DIV 16 16 Ring Counter CTR DIV 16
1D 4 LDCK C1
S R 18 UNCK C1 1D
11 RST
RAM 16 × 5 EN 16 16 1A 2A 1 16 1 16
C3 D0 D1 D2 D3 D4 5 6 7 8 9 1A, 3D 2A 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4
16
16 P Q
COMP P=Q P=Q+2 P=Q2 S
17 EMPTY 3 R 2 FULL1 19 EMPTY+1 FULL
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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