|
Details, datasheet, quote on part number:SN74ALS234N
| |
Datasheet text preview:
SN74ALS234 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS106B OCTOBER 1986 REVISED SEPTEMBER 1993
D D D D D
Asynchronous Operation Organized as 64 Words by 4 Bits Data Rates From 0 to 30 MHz 3-State Outputs Package Options Include Plastic Small-Outline Packages (DW), Plastic J-Leaded Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N)
DW OR N PACKAGE (TOP VIEW)
description
The SN74ALS234 is a 256-bit memory utilizing advanced low-power Schottky IMPACTTM technology. It features high speed with fast fall-through times and is organized as 64 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS234 is designed to process data at rates from 0 to 30 MHz in a bit-parallel format, word by word.
OE IR SI D0 D1 D2 D3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC SO OR Q0 Q1 Q2 Q3 RST
FN PACKAGE (TOP VIEW)
SI D0 NC D1 D2
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
IR OE NC VCC SO OR Q0 NC Q1 Q2
Copyright © 1993, Texas Instruments Incorporated
Data is written into memory on the rising edge of the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words NC No internal connection stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low. Status of the SN74ALS234 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full. When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3). When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output (see Figure 4).
D3 GND NC RST Q3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74ALS234 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS106B OCTOBER 1986 REVISED SEPTEMBER 1993
description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is high. OE does not affect the IR or OR. The SN74ALS234 is characterized for operation from 0°C to 70°C.
logic symbol
FIFO 64 × 4 3 15 CTR 5 + /C1 G2 SO 4 G3 2CT 0 (CT > 0) G4 2 IR 14
SI
OR
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
functional block diagram
D0 D1 D2 D3 4 5 6 7 13 12 11 10 Q0 Q1 Q2 Q3
FIFO Input Stage
62 × 4 Bit Register
FIFO Output Stage
IR SI RST
2 3 9
InputControl Logic
RegisterControl Logic
OutputControl Logic
15 14
SO OR
Pin numbers shown are for the DW and N packages.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALS234 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS106B OCTOBER 1986 REVISED SEPTEMBER 1993
Q0
Word 3
Word 2
Word 1
logic diagram (positive logic)
Word 64
Word 63
D0
D1 D2 D3
Words 4 6 Same as 3 or 63
RST
OE
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SI Data Inputs
SO OR IR
Q1 Q2 Q3
Data Outputs 3
|
|
