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Details, datasheet, quote on part number:SN74ALS373ADBLE
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Datasheet text preview:
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
D D D D D
Eight Latches in a Single Package 3-State Bus-Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines
SN54ALS373A, . . . J OR W PACKAGE SN54AS373 . . . J PACKAGE SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE (TOP VIEW)
description
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE
SN54ALS373A, SN54AS373 . . . FK PACKAGE (TOP VIEW)
OE VCC
1D 1Q
2D 2Q 3Q 3D 4D
3 4 5 6 7 8
2 1 20 19 18 17 16 15
8Q 8D 7D 7Q 6Q 6D
14 9 10 11 12 13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
4Q GND LE 5Q 5D
1
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
ORDERING INFORMATION
TA PDIP N PACKAGE Tube Tube 0°C to 70°C to 70°C SOIC DW DW Tape and reel Tube Tape and reel SOP NS NS CDIP J 55°C to 125°C CFP W LCCC FK FK Tape and reel and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ALS373AN SN74AS373N SN74ALS373ADW SN74ALS373ADWR SN74AS373DW SN74AS373DWR SN74ALS373ANSR SN74AS373NSR SNJ54ALS373AJ SNJ54AS373J SNJ54ALS373AW SNJ54ALS373AFK SNJ54AS373FK TOP-SIDE MARKING SN74ALS373AN SN74AS373N ALS373A AS373 ALS373A 74AS373 SNJ54ALS373AJ SNJ54AS373J SNJ54ALS373AW SNJ54ALS373AFK SNJ54AS373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE LE 1 11
C1 1D 3 1D
2
1Q
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature range (SN54ALS373A, SN74ALS373A) (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, JA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54ALS373A MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.7 1 12 125 0 NOM 5 MAX 5.5 SN74ALS373A MIN 4.5 2 0.8 2.6 24 70 NOM 5 MAX 5.5 UNIT V V V mA mA °C
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
SN54ALS373A MIN fclock tw tsu th Clock frequency Pulse duration, LE high Setup time, data before LE Hold time, data after LE 12 10 7 10 10 7 MAX SN74ALS373A MIN MAX UNIT MHz ns ns ns
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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