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Details, datasheet, quote on part number:SN74ALS845NT
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Datasheet text preview:
SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SDAS233A DECEMBER 1983 REVISED JANUARY 1995
· · · · · ·
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses With Parity Buffered Control Inputs to Reduce dc Loading Effects Power-Up High-Impedance State Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs
DW OR NT PACKAGE (TOP VIEW)
description
OE1 OE2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC OE3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. Because the clear (CLR) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low causes the eight Q outputs to go low. Taking PRE low causes the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. The output enables do not affect the internal operation of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. The SN74ALS845 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS PRE L H H H H X X X CLR X L H H H X X X OE1 L L L L L X X H OE2 L L L L L X H X OE3 L L L L L H X X LE X X H H L X X X D X X L H L X X X OUTPUT Q H L L H Q0 Z Z Z
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SDAS233A DECEMBER 1983 REVISED JANUARY 1995
logic symbol
OE1 OE2 OE3 PRE 11 CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 13 3 4 5 6 7 8 9 10 23 14 S2 R C1 1D 22 2 21 20 19 18 17 16 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1 2 & EN
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE1 OE2 OE3 PRE 14 1 2 23
CLR
11
LE
13 S2
1D
3
C1 1D R 2
22 1Q
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SDAS233A DECEMBER 1983 REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN VCC VIH VIL IOH IOL tw tsu th Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current output current Pulse duration duration Setup time, data before LE Hold time, data after LE CLR or PRE low LE high 35 20 10 5 0 70 4.5 2 0.8 2.6 24 48 NOM 5 MAX 5.5 UNIT V V V mA mA ns ns ns °C
TA Operating free-air temperature Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V II = 18 mA IOH = 0.4 mA IOH = 2.6 mA IOL = 12 mA IOL = 24 mA IOL = 48 mA VO = 2.7 V VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V Outputs high ICC Outputs low Outputs disabled 30 21 41 25 MIN VCC 2 2.4 TYP§ MAX 1.2 3.2 0.25 0.35 0.35 0.4 0.5 0.5 20 20 0.1 20 0.1 112 36 67 42 mA µA µA mA µA mA mA V UNIT V V
VOL IOZH IOZL II IIH IIL IO¶
Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V § All typical values are at VCC = 5 V, TA = 25°C. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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