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Details, datasheet, quote on part number:SN74ALVC16834
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Datasheet text preview:
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140E JULY 1998 REVISED MAY 2002
D D D
Member of the Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140E JULY 1998 REVISED MAY 2002
GQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K Y1 Y3 Y5 Y7 Y9 Y10 Y12 Y14 Y16 Y18 2 NC Y2 Y4 Y6 Y8 Y11 Y13 Y15 Y17 OE GND VCC GND LE GND VCC GND GND 3 NC GND VCC GND 4 GND GND VCC GND 5 NC A2 A4 A6 A8 A11 A13 A15 A17 CLK 6 A1 A3 A5 A7 A9 A10 A12 A14 A16 A18
NC No internal connection
ORDERING INFORMATION
TA PACKAGE SSOP DL DL 40°C to 85°C TSSOP DGG TVSOP DGV VFBGA GQL Tube Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74ALVC16834DL SN74ALVC16834DLR SN74ALVC16834DGGR SN74ALVC16834DGVR SN74ALVC16834GQLR TOP-SIDE MARKING ALVC16834 ALVC16834 VC834
VC834 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE H L L L L L LE X L L H H H CLK X X X H A X L H L H X OUTPUT Y Z L H L H Y0 Y0§
L H L X Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high § Output level before the indicated steady-state input conditions were established
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140E JULY 1998 REVISED MAY 2002
logic diagram (positive logic)
OE 27
CLK
30
LE
28
A1
54
1D C1 CLK 3 Y1
To 17 Other Channels Pin numbers shown are for the DGG, DGV, and DL packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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