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Part: SN74ALVCH16601DLR
Category:
Logic
-> Transceivers
-> Universal Bus Transceivers (UBTs)
Description: ti SN74ALVCH16601, 18-Bit Universal Bus Transceiver With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download SN74ALVCH16601DLR datasheet File size : 138 kB
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Datasheet text preview:
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES027E JULY 1995 REVISED MAY 2000
D D D D D D D
Member of the Texas Instruments Widebus TM Family UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
description
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by 27 30 output-enable (OEAB and OEBA), latch-enable 28 29 (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16601 is characterized for operation from 40°C to 85°C.
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES027E JULY 1995 REVISED MAY 2000
FUNCTION TABLE INPUTS CLKENAB X X X H H L L L L OEAB H L L L L L L L L LEAB X H H L L L L L L CLKAB X X X X X H L A X L H X X L H X X OUTPUT B Z L H B0 B0 L H B0
B0§ A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low § Output level before the indicated steady-state input conditions were established
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES027E JULY 1995 REVISED MAY 2000
logic diagram (positive logic)
OEAB 1
CLKENAB
56
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
CLKENBA
29
OEBA
27 CE 1D C1 CLK CE 1D C1 CLK 54 B1
A1
3
To 17 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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