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Details, datasheet, quote on part number:SN74ALVTH162245LR
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Datasheet text preview:
SN54ALVTH162245, SN74ALVTH162245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES331A APRIL 2000 REVISED APRIL 2002
D D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive A Port = 12/12 mA at 3.3-V VCC B port = 32/64 mA at 3.3-V VCC Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating A-Port Outputs Have Equivalent 30- Series Resistors, So No External Resistors Are Required Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
SN54ALVTH162245 . . . WD PACKAGE SN74ALVTH162245 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE
description
The 'ALVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 30- series resistors to reduce overshoot and undershoot. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2002, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ALVTH162245, SN74ALVTH162245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES331A APRIL 2000 REVISED APRIL 2002
description (continued)
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74ALVTH162245 . . . GQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K 1DIR 1B2 1B4 1B6 1B8 2B1 2B3 2B5 2B7 2DIR 2 NC 1B1 1B3 1B5 1B7 2B2 2B4 2B6 2B8 NC GND VCC GND NC GND VCC GND NC 3 NC GND VCC GND 4 NC GND VCC GND 5 NC 1A1 1A3 1A5 1A7 2A2 2A4 2A6 2A8 NC 6 1OE 1A2 1A4 1A6 1A8 2A1 2A3 2A5 2A7 2OE
NC No internal connection
ORDERING INFORMATION
TA PACKAGE SSOP DL 40°C to 85°C to 85°C TSSOP DGG TVSOP DGV VFBGA GQL 55°C to 125°C CFP WD Tape and reel Tape and reel Tape and reel Tape and reel Tube ORDERABLE PART NUMBER SN74ALVTH162245LR SN74ALVTH162245GR SN74ALVTH162245VR SN74ALVTH162245QR TOP-SIDE MARKING ALVTH162245 ALVTH162245 VT2245
SNJ54ALVTH162245WD SNJ54ALVTH162245WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 8-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES331A APRIL 2000 REVISED APRIL 2002
logic diagram (positive logic)
1DIR 1 2DIR 48 24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels Pin numbers shown are for the DGG, DGV, DL, and WD packages.
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output current in the low state, IO: SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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