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Details, datasheet, quote on part number:SN74ALVTH16240DGG
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Datasheet text preview:
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES138A JULY 1998 REVISED JANUARY 1999
D D D D D D D D D D
D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (24/24 mA at 2.5-V and 32/64 mA at 3.3-V VCC) Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16240 . . . WD PACKAGE SN74ALVTH16240 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
1OE 1Y1 1Y2 GND 1Y3 1Y4 VC C 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VC C 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
description
The 'ALVTH16240 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1999, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES138A JULY 1998 REVISED JANUARY 1999
description (continued)
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide inverting outputs and symmetrical active-low output-enable (OE) inputs. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16240 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALVTH16240 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y L H Z
logic symbol
1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1 48 25 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 1 2 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES138A JULY 1998 REVISED JANUARY 1999
logic diagram (positive logic)
1OE 1 3OE 2 25
1A1
47
1Y1
3A1
36
13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE
48
4OE 8
24
2A1
41
2Y1
4A1
30
19
4Y1
2A2
40
9
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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