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Details, datasheet, quote on part number:SN74ALVTH16244VR
 
 
Part:SN74ALVTH16244VR
Category:Logic => Buffers/Drivers => Non-Inverting Buffers and Drivers
Description:ti SN74ALVTH16244, 2.5-V/3.3-V 16-Bit Buffers/drivers With 3-State Outputs
Company:Texas Instruments, Inc.
Datasheet:Download SN74ALVTH16244VR datasheet   File size : 162 kB
Request For quote:  Find where to buy SN74ALVTH16244VR
 



Datasheet text preview:
SN54ALVTH16244, SN74ALVTH16244 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES070G ­ JUNE 1996 ­ REVISED MAY 1999

D D D D D D D D D D D D D

Members of the Texas Instruments Widebus TM Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation 5-V I/O Compatible High Drive Capability (­32 mA/64 mA) Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Auto3-State Eliminates Bus Current Loading When Voltage at the Output Exceeds VCC Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

SN54ALVTH16244 . . . WD PACKAGE SN74ALVTH16244 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)

1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE

NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

description
The 'ALVTH16244 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

Copyright © 1999, Texas Instruments Incorporated

· DALLAS, TEXAS 75265

1

SN54ALVTH16244, SN74ALVTH16244 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES070G ­ JUNE 1996 ­ REVISED MAY 1999

description (continued)
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54ALVTH16244 is characterized for operation over the full military temperature range of ­55°C to 125°C. The SN74ALVTH16244 is characterized for operation from ­40°C to 85°C.
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z

logic diagram (positive logic)
1OE 1 3OE 2 25

1A1

47

1Y1

3A1

36

13

3Y1

1A2

46

3

1Y2

3A2

35

14

3Y2

1A3

44

5

1Y3

3A3

33

16

3Y3

1A4

43

6

1Y4

3A4

32

17

3Y4

2OE

48

4OE 8

24

2A1

41

2Y1

4A1

30

19

4Y1

2A2

40

9

2Y2

4A2

29

20

4Y2

2A3

38

11

2Y3

4A3

27

22

4Y3

2A4

37

12

2Y4

4A4

26

23

4Y4

2

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

SN54ALVTH16244, SN74ALVTH16244 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES070G ­ JUNE 1996 ­ REVISED MAY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . ­0.5 V to VCC to 7V Output current in the low state, IO: SN54ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­48 mA SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16244 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 0 2.3 1.7 0.7 5.5 ­6 6 18 10 200 0 MAX 2.7 SN74ALVTH16244 MIN 2.3 1.7 0.7 5.5 ­8 8 24 10 MAX 2.7 UNIT V V V V mA mA ns/V µs/V

TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

3

SN54ALVTH16244, SN74ALVTH16244 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES070G ­ JUNE 1996 ­ REVISED MAY 1999

recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16244 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 0 3 2 0.8 5.5 ­24 24 48 10 200 0 MAX 3.6 SN74ALVTH16244 MIN 3 2 0.8 5.5 ­32 32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V µs/V

TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

4

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

SN54ALVTH16244, SN74ALVTH16244 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCES070G ­ JUNE 1996 ­ REVISED MAY 1999

electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS CONDITIONS VCC = 2.3 V, VCC = 2.3 V to 2.7 V, VCC = 2 3 V 2.3 VCC = 2.3 V to 2.7 V, VOL II = ­18 mA IOH = ­100 µA IOH = ­6 mA IOH = ­8 mA IOL = 100 µA IOL = 6 mA IOL = 8 mA IOL = 18 mA IOL = 24 mA VI = VCC or GND VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.7 V VI = 1.7 V VI = 0 to 2.7 V VO = 5.5 V 115 ­10 ±300 125 ±100 5 ­5 0.04 2.3 0.04 3 0.1 4.5 0.1 0.04 2.3 0.04 3 SN54ALVTH16244 MIN TYP MAX ­1.2 VCC­0.2 1.8 0.2 0.4 0.4 0.5 0.5 ±1 10 1 ­5 115 ­10 ±300 125 ±100 5 ­5 0.1 4.5 0.1 pF mA µA µA µA µA µA ±1 10 1 ­5 ±100 µA µA V VCC­0.2 V 1.8 0.2 SN74ALVTH16244 MIN TYP MAX ­1.2 UNIT V

VCC = 2 3 V 2.3

Control inputs inputs II Data inputs inputs Ioff II(hold) IEX§ IOZ(PU/PD)¶ IOZH IOZL Data inputs

VCC = 2.7 V, VCC = 0 or 2.7 V, VCC = 2 7 V 2.7 VCC = 0, VCC = 2 3 V 2.3 VCC = 2.7 V, VCC = 2.3 V,

VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 2.7 V VCC = 2.7 V VCC = 2.7 V, 2.7 V, IO = 0, VI = VCC or GND VCC = 2.5 V, VCC = 2.5 V, VO = 2.3 V, VI = 0.7 V or 1.7 V VO = 0.5 V, VI = 0.7 V or 1.7 V Outputs high Outputs low Outputs disabled VI = 2.5 V or 0 VO = 2.5 V or 0

ICC Ci

Co 6 6 pF All typical values are at VCC = 2.5 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § Current into an output in the high state when VO > VCC ¶ High-impedance state during power up/power down

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

5