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Details, datasheet, quote on part number:SN74ALVTH16245
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Datasheet text preview:
SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
SN54ALVTH16245 . . . WD PACKAGE SN74ALVTH16245 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
The 'ALVTH16245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2002, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
1
SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
SN74ALVTH16245 . . . GQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K 1DIR 1B2 1B4 1B6 1B8 2B1 2B3 2B5 2B7 2DIR 2 NC 1B1 1B3 1B5 1B7 2B2 2B4 2B6 2B8 NC GND VCC GND NC GND VCC GND NC 3 NC GND VCC GND 4 NC GND VCC GND 5 NC 1A1 1A3 1A5 1A7 2A2 2A4 2A6 2A8 NC 6 1OE 1A2 1A4 1A6 1A8 2A1 2A3 2A5 2A7 2OE
NC No internal connection
ORDERING INFORMATION
TA PACKAGE SSOP DL 40°C to 85°C to 85°C TSSOP DGG TVSOP DGV VFBGA GQL Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74ALVTH16245DLR SN74ALVTH16245GR SN74ALVTH16245VR SN74ALVTH16245QR TOP-SIDE MARKING ALVTH16245 ALVTH16245 VT245
55°C to 125°C CFP WD Tube SNJ54ALVTH16245WD SNJ54ALVTH16245WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 8-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
logic diagram (positive logic)
1DIR 1 2DIR 48 24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels Pin numbers shown are for the DGG, DGV, DL, and WD packages.
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . 0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16245 MIN VCC VIH VIL VI IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Outputs enabled 0 VCC 2.3 1.7 0.7 5.5 6 6 18 10 0 VCC TYP MAX 2.7 SN74ALVTH16245 MIN 2.3 1.7 0.7 5.5 8 8 24 10 TYP MAX 2.7 UNIT V V V V mA mA ns/V
t/VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16245 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1 kHz Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 0 VCC 3 2 0.8 5.5 24 24 48 10 200 0 VCC TYP MAX 3.6 SN74ALVTH16245 MIN 3 2 0.8 5.5 32 32 64 10 TYP MAX 3.6 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS CONDITIONS VCC = 2.3 V, VCC = 2.3 V to 2.7 V, VCC = 2 3 V 2.3 VCC = 2.3 V to 2.7 V, VOL II = 18 mA IOH = 100 µA IOH = 6 mA IOH = 8 mA IOL = 100 µA IOL = 6 mA IOL = 8 mA IOL = 18 mA IOL = 24 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.7 V VI = 1.7 V VI = 0 to VCC VI = 0 to VCC VO = 5.5 V 300 300 125 ±100 0.04 2.3 0.04 3.5 8 0.1 4.5 0.1 0.04 2.3 0.04 3.5 8 115 10 300 300 125 ±100 0.1 4.5 0.1 pF mA SN54ALVTH16245 MIN TYP MAX 1.2 VCC0.2 1.8 0.2 0.4 0.4 0.5 0.5 ±1 10 20 1 5 115 10 ±1 10 20 1 5 ±100 µA µA µA µA µA µA µA µA V VCC0.2 V 1.8 0.2 SN74ALVTH16245 MIN TYP MAX 1.2 UNIT V
VCC = 2 3 V 2.3
Control inputs inputs II A or B ports Ioff IBHL IBHH§ IBHLO¶ IBHHO# IEX|| IOZ(PU/PD)k
VCC = 2.7 V, VCC = 0 or 2.7 V, VCC = 2.7 V VCC = 0, VCC = 2.3 V, VCC = 2.3 V, VCC = 2.7 V, VCC = 2.7 V, VCC = 2.3 V,
VCC 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don't care VCC = 2.7 V, 2.7 V, IO = 0, VI = VCC or GND VCC = 2.5 V, VCC = 2.5 V, Outputs high Outputs low Outputs disabled VI = 2.5 V or 0 VO = 2.5 V or 0
ICC Ci Cio
pF All typical values are at VCC = 2.5 V, TA = 25°C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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