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Details, datasheet, quote on part number:SN74AS163N
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Datasheet text preview:
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
D D D D D
Internal Look-Ahead Circuitry for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) DIPs
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . J PACKAGE SN74ALS161B, SN74AS161, SN74AS163 . . . D OR N PACKAGE SN74ALS163B . . . D, DB, OR N PACKAGE (TOP VIEW)
description
These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The 'ALS161B, 'ALS163B, 'AS161, and 'AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RCO QA QB QC QD ENT LOAD
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . FK PACKAGE (TOP VIEW)
A B NC C D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLK CLR NC VCC RCO QA QB NC QC QD
NC No internal connection
Copyright © 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
The clear function for the 'ALS161B and 'AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, 'ALS163B, and 'AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 ( LLLL ). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
ENP GND NC LOAD ENT
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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
description (continued)
produces a high-level pulse while the count is maximum (9 or 15, with QA high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
logic symbols
'ALS161B AND 'AS161 BINARY COUNTERS WITH DIRECT CLEAR 1 CLR LOAD ENT ENP CLK A B C D 10 7 2 3 4 5 6 9 CTRDIV16 CT=0 M1 M2 G3 G4 C5/2,3,4+ 1, 5D [1] [2] [4] [8] 14 13 12 11 QA QB QC QD 15 'ALS163B AND 'AS163 BINARY COUNTERS WITH SYNCHRONOUS CLEAR 1 CLR LOAD RCO ENT ENP CLK A B C D 10 7 2 3 4 5 6 9 CTRDIV16 5CT=0 M1 M2 G3 G4 C5/2,3,4+ 1, 5D [1] [2] [4] [8] 14 13 12 11 QA QB QC QD 15
3CT=15
3CT=15
RCO
SN54ALS162B DECADE COUNTER WITH SYNCHRONOUS CLEAR 1 CLR LOAD ENT ENP CLK A B C D 10 7 2 3 4 5 6 9 CTRDIV10 5CT=0 M1 M2 G3 G4 C5/2,3,4+ 1, 5D [1] [2] [4] [8] 14 13 12 11 QA QB QC QD 15
3CT=9
RCO
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, and N packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
logic diagram (positive logic)
LOAD ENT ENP CLR 9 10 7 1 SN54ALS162B
15
RCO
CLK
2 C1 1D 3 14 QA
A
C1 1D
13
QB
B
4
C1 1D
12
QC
C
5
C1 1D
11
QD
D
6
Pin numbers shown are for the J package.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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