|
Details, datasheet, quote on part number:SN74AS877NT
| |
| Part: | SN74AS877NT |
| Category: | Logic => Transceivers => Universal Bus Transceivers (UBTs) |
| Description: | ti SN74AS877, 8-Bit Universal Transceiver Port Controllers |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74AS877NT datasheet File size : 145 kB |
| Request For quote: | Find where to buy SN74AS877NT
|
| |
Datasheet text preview:
SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS
SDAS234 D2661, DECEMBER 1982 REVISED AUGUST 1985
· · · ·
· ·
·
Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Buffered 3-State Outputs Drive Bus Lines Directly Cascaded to n-Bits Eight Selectable Transceiver/Port Functions: A to B or B to A Register to A or Register to B Shifted to A or Shifted to B Off-Line Shifts (A and B Ports in High-Impedance State) Register Clear Particularly Suitable for Use in Signature Analysis Circuitry Serial Register Provides: Parallel Storage of Either A or B Input Data Serial Transmission of Data from Either A or B Port Dependable Texas Instruments Quality and Reliability
SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW)
S0 S1 S2 A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLK SERIN B1 B2 B3 B4 B5 B6 B7 B8 Q8
SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW)
S2 S1 S0 NC VCC CLK SERIN A1 A2 A3 NC A4 A5 A6
5 6 7 8 4 3 2 1 28 27 26 25 24 23 22
description
9 21 The 'AS877 features two 8-bit I/O ports (A1-A8 10 and B1-B8), an 8-bit parallel-load, serial-in, 20 parallel-out shift register, and control logic. With 11 19 12 13 14 15 16 17 18 these features, this device is capable of performing eight selectable transceiver or port functions, depending on the state of the three select lines S0, S1, and S2. These functions NC No internal connection include: transferring data from port A to port B or vice versa (i.e., the transceiver function), transferring data from the register to either port, serial shifting data to either port, performing off-line shifts (with A and B ports in high-impedance state), and clearing the register. Synchronous parallel loading of the internal register can be accomplished from either port on the positive transition of the clock while serially shifting data in via the SERIN input. The 'AS877 is ideally suited for applications needing signature-analysis circuitry to enhance system verification and/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specifically to drive bus lines directly and all are 3-state except for Q8, which is a totem-pole output.
B1 B2 B3 NC B4 B5 B6
The SN54AS877 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS877 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A7 A8 GND NC Q8 B8 B7
Copyright © 1985, Texas Instruments Incorporated
1
SDAS234 D2661, DECEMBER 1982 REVISED AUGUST 1985
SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS
FUNCTION TABLE
MODE CLOCK S2 L L L L L L L L H H H S1 L L L L H H H H L L L L L L H H H H H S0 L L H H L L H H L L L H H H L L L H H H or L H or L H or L H or L H or L H or L H or L H or L X X X X X X X X X H L X H L X H L X H Z Z B1 B1 X Z Q1 B1 Z Z Z Q1 H L Z Z Z Z Z Qn A1 Qn B1 Qn A1 Qn B1 Qn H L Qn H L Qn H L Qn H A1 A1 Z Z Q1 A1 X Z Q1 H L Z Z Z Z Z Z Z Z Z Z B2 B2 X Z Q2 B2 Z Z Z Q2 Q1 Q1 Z Z Z Z Z Qn A2 Qn B2 Qn A2 Qn B2 Qn Q1 Q1 Qn Q1 Q1 Qn Q1 Q1 Qn L A2 A2 Z Z Q2 A2 X Z Q2 Q1 Q1 Z Z Z Z Z Z Z Z Z Z B3 B3 X Z Q3 B3 Q3 Q2 Q2 Q3 Q2 Q2 Z Z Z Z Z Qn A3 Qn B3 Qn A3 Qn B3 Qn Q2 Q2 Qn Q2 Q2 Qn Q2 Q2 Qn L A3 A3 Z Z Q3 A3 Z Z Q3 Q2 Q2 Z Z Z Z Z Z Z Z Z Z B4 B4 X Z Q4 B4 Z Z Z Q4 Q3 Q3 Z Z Z Z Z Qn A4 Qn B4 Qn A4 Qn B4 Qn Q3 Q3 Qn Q3 Q3 Qn Q3 Q3 Qn L Q4 Q4 Z Z Q4 A4 Z Z Q4 Q3 Q3 Z Z Z Q4 Q3 Q3 Z Z Z Z B5 B5 X Z Q5 B5 Z Z Z Q5 Q4 Q4 Z Z Z Z Z Qn Q5 Qn B5 Qn A5 Qn B5 Qn Q4 Q4 Qn Q4 Q4 Qn Q4 Q4 Qn L A5 A5 Z Z Q5 A5 X Z Q5 Q4 Q4 Z Z Z Z Z Z Z Z Z Z B6 B6 X Z Q6 B6 Z Z Z Q6 Q5 Q5 Z Z Z Z Z Qn A6 Qn B6 Qn A6 Qn B6 Qn Q5 Q5 Qn Q5 Q5 Qn Q5 Q5 Qn L Q6 Q6 Z Z Q6 A6 Z Z Q6 Q5 Q5 Z Z Z Q6 Q5 Q5 Z Z Z Z B7 B7 X Z Q7 B7 Z Z Z Q7 Q6 Q6 Z Z Z Z Z Qn A7 Qn B7 Qn A7 Qn B7 Qn Q6 Q6 Qn Q6 Q6 Qn Q6 Q6 Qn L Q7 Q7 Z Z Q7 A7 Z Z Q7 Q6 Q6 Z Z Z Q7 Q6 Q6 Z Z Z Z B8 B8 X Z Q8 B8 Z Z Z Q8 Q7 Q7 Z Z Z Z Z Qn A8 Qn B8 Qn A8 Qn B8 Qn Q7 Q7 Qn Q7 Q7 Qn Q7 Q7 Qn L A8 A To B To A8 Z B To A To Z Q8 A8 X Z Q8 Q7 Q7 Z Z Z Z Z Z Z Clear Z Shift QN To AN To Shift To B Shift To A QN To BN To SERIN A1 Q1 B1 A2 Q2 B2 A3 Q3 B3 A4 Q4 B4 A5 Q5 B5 A6 Q6 B6 A7 Q7 B7 A8 Q8 B8 PORT FUNCTION
2
POST OFFICE BOX 1443 · HOUSTON, TEXAS 77001 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 H H H H H H H H
n = level Of Qn(n = 1, 2 . . . 8) established on most recent transition of CLK. Q1 thru Q8 are the shift register outputs; only Q8 is available externally. The double inversions that take place as data travels from port to port are ignored in this table.
SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 D2661, DECEMBER 1982 REVISED AUGUST 1985
logic symbol
1 S0 2 S1 3 S2 23 CLK 22 SERIN 4 A1 (PORT CONTROLLER) 0 2 Z9 1 11 12 (1/3/5) 13,1 13 14,(3/5) 1 Z15 15 (1/3/5) 16 16,1 17(3/5) Z11 Z12 0 EN 7 9 9 SRG8 (4/5/6) C10/7R I=0 (4/5/6)10D (0/2)10D 12 (1/3)10D I=0 (0/2)10D 15 (1/3)10D 1 (0/2/4) 0 Z13 2/4 Z14 1 (0/2/4) 0 Z16 2/4 Z17 21 B1
A2
5
20
B2
A3 A4 A5 A6 A7 A8
6 7 8 9 10 11
19 18 17 16 15 14 13
B3 B4 B5 B6 B7 B8 Q8
1 33 (1/3/5) 34,1 34 35(3/5) Z33
I=0 (0/2)10D 33 (1/3)10D
1 (0/2/4) Z34 0 35 2/4 Z35
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
·
·
3
|
|
