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Details, datasheet, quote on part number:SN74AS885NT3
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Datasheet text preview:
SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
· · · · · · ·
Latchable P-Input Ports With Power-Up Clear Choice of Logical or Arithmetic (Two's Complement) Comparison Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects Approximately 35% Improvement in ac Performance Over Schottky TTL While Performing More Functions Cascadable to n Bits While Maintaining High Performance 10% Less Power Than STTL for an 8-Bit Comparison Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS885 . . . JT PACKAGE SN74AS885 . . . DW OR NT PACKAGE (TOP VIEW)
L/A P QIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC PLE P7 P6 P5 P4 P3 P2 P1 P0 P QOUT
SN54AS885 . . . FK PACKAGE (TOP VIEW)
These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.
Q7 Q6 Q5 NC Q4 Q3 Q2
P > QIN P < QIN L/A NC VCC PLE P7
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
description
P6 P5 P4 NC P3 P2 P1
NC No internal connection
The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically 0.25 mA, which minimizes dc loading effects. The SN54AS885 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Q1 Q0 GND NC P > QOUT P < QOUT P0
Copyright © 1995, Texas Instruments Incorporated
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SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
FUNCTION TABLE INPUTS COMPARISON L/A H H H L L DATA P0 P7, Q0 Q7 P>Q P QIN X X H or L X X P QOUT H L H or L H L P < QOUT L H H or L L H
Logical Logical Logical Arithmetic Arithmetic Arithmetic
L P=Q H or L H or L H or L H or L In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN. AG = arithmetically greater than
logic symbol
L/A PLE P0 P1 P2 P3 P4 P5 P6 P7 P > QIN P Q 7 P QOUT P < QOUT P COMP M [LOGIC] M [ARITH, 2s COMP] C1 1D 1=0 0
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS
SDAS236A DECEMBER 1982 REVISED JANUARY 1995
logic diagram (positive logic)
PLE P7 P6 23 22
1D C1
P7 = Q7 P7 P7 P6 P6 P5 P5 P4 P4 P3 P3 P2 P2 P5 = Q5 P6 = Q6
21 20 19 18 17 16 15
P5 P4 P3 P2 P1
P3 = Q3
P2 = Q2 P1 = Q1 14 P < QOUT
P1 P0 = Q0 P1 P0 P0
P0
Q7 Q6
4 5
Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 4MSB = 13 P > QOUT
Q5 6 Q4 7 8
Q3
Q2 9 Q1 10 Q0 11 P > QIN 3 P < QIN 2 1 L/A
Q0
ARITH LOGIC
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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