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Details, datasheet, quote on part number:SN74AUC1G74YEPR
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Datasheet text preview:
SN74AUC1G74 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
SCES537 - DECEMBER 2003
D Available in the Texas Instruments D D D D D D D D
NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.5 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE (TOP VIEW)
CLK D Q GND
1 2 3 4
8 7 6 5
VCC PRE CLR Q
YEP OR YZP PACKAGE (BOTTOM VIEW)
GND Q D CLK
45 36 27 18
Q CLR PRE VCC
description/ordering information
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION
TA PACKAGE NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP -40°C to 85°C NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SSOP - DCT VSSOP - DCU Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74AUC1G74YEPR _ _ _UP_ SN74AUC1G74YZPR SN74AUC1G74DCTR SN74AUC1G74DCUR U74_ _ _ UP_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, · = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCES537 - DECEMBER 2003
SN74AUC1G74 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE INPUTS PRE L X H H H CLR H L H H H CLK X X L D X X H L X OUTPUTS Q H L H L Q0 Q L H L H Q0
logic diagram (positive logic)
PRE CLK 7 1 C
C C
5 TG
Q
C
C C
C
3
Q
D
2
TG
TG
TG
C CLR 6
C
C
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AUC1G74 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
SCES537 - DECEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH Supply voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 0.8 V VCC = 1.1 V IOH High-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 0.8 V IOL Low-level output current VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V t/v Input transition rise or fall rate VCC = 0.8 V to 1.65 V VCC = 1.65 V to 2.3 V§ VCC = 2.3 V to 2.7 V§ VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0 0 0.8 VCC 0.65 × VCC 1.7 0 0.35 × VCC 0.7 3.6 VCC -0.7 -3 -5 -8 -9 0.7 3 5 8 9 20 20 20 ns/V mA mA V V V MAX 2.7 UNIT V
High-level input voltage
V
TA Operating free-air temperature -40 85 °C The data was taken at CL = 15 pF, RL = 2 k (see Figure 1). § The data was taken at CL = 30 pF, RL = 500 (see Figure 1). NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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