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Details, datasheet, quote on part number:SN74AUC1G80
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Datasheet text preview:
SN74AUC1G80 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP
SCES388I - MARCH 2002 - REVISED JUNE 2004
D Available in the Texas Instruments D D D D D D D D
NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.9 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE (TOP VIEW)
D CLK GND
1 2 3
5 4
VCC Q
YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW)
GND CLK D
34 2 15
Q VCC
description/ordering information
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION
TA PACKAGE NanoStar - WCSP (DSBGA) 0.17-mm Small Bump - YEA NanoFree - WCSP (DSBGA) 0.17-mm Small Bump - YZA (Pb-free) -40°C to 85°C NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SOT (SOT-23) - DBV SOT (SC-70) - DCK Tape and reel SN74AUC1G80YZPR Tape and reel Tape and reel SN74AUC1G80DBVR SN74AUC1G80DCKR U80_ UX_ Tape and reel SN74AUC1G80YZAR _ _ _UX_ SN74AUC1G80YEPR ORDERABLE PART NUMBER SN74AUC1G80YEAR TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, · = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74AUC1G80 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP
SCES388I - MARCH 2002 - REVISED JUNE 2004
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE INPUTS CLK L D H L X OUTPUT Q L H Q0
logic diagram (positive logic)
CLK CLK Q D D Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AUC1G80 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP
SCES388I - MARCH 2002 - REVISED JUNE 2004
recommended operating conditions (see Note 3)
MIN VCC VIH Supply voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 0.8 V VCC = 1.1 V IOH High-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 0.8 V VCC = 1.1 V IOL Low-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V t/v Input transition rise or fall rate VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0 0 0.8 VCC 0.65 × VCC 1.7 0 0.35 × VCC 0.7 3.6 VCC -0.7 -3 -5 -8 -9 0.7 3 5 8 9 20 ns/V mA mA V V V MAX 2.7 UNIT V
High-level input voltage
V
TA Operating free-air temperature -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 µA IOH = -0.7 mA VOH IOH = -3 mA IOH = -5 mA IOH = -8 mA IOH = -9 mA IOL = 100 µA IOL = 0.7 mA VOL IOL = 3 mA IOL = 5 mA IOL = 8 mA IOL = 9 mA II Ioff ICC Ci D or CLK input VI = VCC or GND VI or VO = 2.7 V VI = VCC or GND, VI = VCC or GND IO = 0 TEST CONDITIONS VCC 0.8 V to 2.7 V 0.8 V 1.1 V 1.4 V 1.65 V 2.3 V 0.8 V to 2.7 V 0.8 V 1.1 V 1.4 V 1.65 V 2.3 V 0 to 2.7 V 0 0.8 V to 2.7 V 2.5 V 2.5 0.25 0.3 0.4 0.45 0.6 ±5 ±10 10 µA µA µA pF V 0.8 1 1.2 1.8 0.2 V MIN VCC-0.1 0.55 TYP MAX UNIT
All typical values are at TA = 25°C.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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