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Details, datasheet, quote on part number:SN74AUC32244
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Datasheet text preview:
SN74AUC32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES425 FEBRUARY 2003
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Member of the Texas Instruments Widebus+ Family Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.8 ns at 1.8 V
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Low Power Consumption, 40-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
40°C to 85°C LFBGA GKE Tape and reel SN74AUC32244GKER MM244 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74AUC32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES425 FEBRUARY 2003
GKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T 1Y2 1Y4 2Y2 2Y4 3Y2 3Y4 4Y2 4Y3 5Y2 5Y4 6Y2 6Y4 7Y2 7Y4 8Y2 8Y3 2 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y4 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y4 3 1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE 4 2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE 5 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A4 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A4 6 1A2 1A4 2A2 2A4 3A2 3A4 4A2 4A3 5A2 5A4 6A2 6A4 7A2 7A4 8A2 8A3
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AUC32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES425 FEBRUARY 2003
logic diagram (positive logic)
1OE A3 3OE A2 H4
1A1
A5
1Y1
3A1
E5
E2
3Y1
1A2
A6
A1
1Y2
3A2
E6
E1
3Y2
1A3
B5
B2
1Y3
3A3
F5
F2
3Y3
1A4
B6
B1
1Y4
3A4
F6
F1
3Y4
2OE
A4
4OE C2
H3
2A1
C5
2Y1
4A1
G5
G2
4Y1
2A2
C6
C1
2Y2
4A2
G6
G1
4Y2
2A3
D5
D2
2Y3
4A3
H6
H1
4Y3
2A4
D6
D1
2Y4
4A4
H5
H2
4Y4
5OE
J3
7OE J2
T4
5A1
J5
5Y1
7A1
N5
N2
7Y1
5A2
J6
J1
5Y2
7A2
N6
N1
7Y2
5A3
K5
K2
5Y3
7A3
P5
P2
7Y3
5A4
K6
K1
5Y4
7A4
P6
P1
7Y4
6OE
J4
8OE L2
T3
6A1
L5
6Y1
8A1
R5
R2
8Y1
6A2
L6
L1
6Y2
8A2
R6
R1
8Y2
6A3
M5
M2
6Y3
8A3
T6
T1
8Y3
6A4
M6
M1
6Y4
8A4
T5
T2
8Y4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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