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Details, datasheet, quote on part number:SN74AUCH16374GQLR
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Datasheet text preview:
SN74AUCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCES404D JULY 2002 REVISED MAY 2003
D D D D D D D D D D
Member of the Texas Instruments Widebus Family Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 2.8 ns at 1.8 V Low Power Consumption, 20 µA Max ICC ±8-mA Output Drive at 1.8 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE (TOP VIEW)
description/ordering information
This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK
The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION
TA PACKAGE TSSOP DGG 40°C to 85°C TVSOP DGV VFBGA GQL Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74AUCH16374DGGR SN74AUCH16374DGVR SN74AUCH16374GQLR TOP-SIDE MARKING AUCH16374 MJ374 MJ374
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74AUCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCES404D JULY 2002 REVISED MAY 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6 A B C D E F G H J K
terminal assignments
1 1OE 1Q2 1Q4 1Q6 1Q8 2Q1 2Q3 2Q5 2Q7 2OE 2 NC 1Q1 1Q3 1Q5 1Q7 2Q2 2Q4 2Q6 2Q8 NC GND VCC GND NC GND VCC GND NC 3 NC GND VCC GND 4 NC GND VCC GND 5 NC 1D1 1D3 1D5 1D7 2D2 2D4 2D6 2D8 NC 6 1CLK 1D2 1D4 1D6 1D8 2D1 2D3 2D5 2D7 2CLK
NC No internal connection FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
1OE 1CLK 1 48 C1 1D 2 1Q1 2OE 2CLK 24 25 C1 2D1 36 1D 13
1D1
47
2Q1
To Seven Other Channels Pin numbers shown are for the DGG and DGV packages.
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AUCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SCES404D JULY 2002 REVISED MAY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH Supply voltage High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL VI VO Low-level input voltage Input voltage Output voltage voltage Active state 3-state VCC = 0.8 V VCC = 1.1 V IOH High-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 0.8 V IOL Low-level output current VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V t/v Input transition rise or fall rate VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0 0 0 0.8 VCC 0.65 × VCC 1.7 0 0.35 × VCC 0.7 3.6 VCC 3.6 0.7 3 5 8 9 0.7 3 5 8 9 20 ns/V mA mA V V V V MAX 2.7 UNIT V V
TA Operating free-air temperature 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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