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Details, datasheet, quote on part number:SN74AVC32373GKE
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Datasheet text preview:
SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCES327 APRIL 2000
D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process DOC TM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
D D D D D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Packaged in Plastic Fine-Pitch Ball Grid Array Package
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
3.2 2.8 VOL Output Voltage V 2.4 2.0 1.6 VCC = 2.5 V 1.2 VCC = 1.8 V 0.8 0.4 0 17 34 51 68 85 102 119 IOL Output Current mA 136 153 170 VCC = 3.3 V TA = 25°C Process = Nominal Output Voltage V TA = 25°C Process = Nominal
2.8 2.4 2.0 1.6 1.2 0.8
V
OH
VCC = 3.3 V 0.4
VCC = 2.5 V VCC = 1.8 V 32 16 0
160 144 128 112 96 80 64 48 IOH Output Current mA
Figure 1. Output Voltage vs Output Current This 32-bit transparent D-type latch with is operational from 1.2-V or 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC32373 can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCES327 APRIL 2000
description (continued)
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC32373 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 8-bit latch) INPUTS OE L L L H GKE PACKAGE (TOP VIEW) LE H H L X D H L X X OUTPUT Q H L Q0 Z
1 A B C D E F G H J K L M N P R T
2
3
4
5
6
terminal assignments
1 A B C D E F G H J K L M N P R T 1Q2 1Q4 1Q6 1Q8 2Q2 2Q4 2Q6 2Q7 3Q2 3Q4 3Q6 3Q8 4Q2 4Q4 4Q6 4Q7 2 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q8 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q8 3 1OE GND 1VCC GND GND 1VCC GND 2OE 3OE GND 2VCC GND GND 2VCC GND 4OE 4 1LE GND 1VCC GND GND 1VCC GND 2LE 3LE GND 2VCC GND GND 2VCC GND 4LE 5 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D8 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D8 6 1D2 1D4 1D6 1D8 2D2 2D4 2D6 2D7 3D2 3D4 3D6 3D8 4D2 4D4 4D6 4D7
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74AVC32373 1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCES327 APRIL 2000
logic diagram (positive logic)
1OE 1LE A3 A4 C1 1D1 A5 1D A2 2OE 2LE 1Q1 H3 H4 C1 2D1 E5 1D E2
2Q1
To Seven Other Channels NOTE A: 1VCC is associated with these channels. J3 J4 C1 3D1 J5 1D J2 T3 T4
To Seven Other Channels
3OE 3LE
4OE 4LE 3Q1
C1 4D1 N5 1D
N2
4Q1
To Seven Other Channels NOTE B: 2VCC is associated with these channels.
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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