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Details, datasheet, quote on part number:SN74BCT29834
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Datasheet text preview:
SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 SEPTEMBER 1987 REVISED NOVEMBER 1993
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BiCMOS Process With TTL Inputs and Outputs BiCMOS Design Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to SN74ALS29834 and AMD Am29834 High-Speed Bus Transceiver With Parity Generator / Checker Parity-Error Flag With Open-Collector Output Available Register For Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
DW OR NT PACKAGE (TOP VIEW)
OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK
description
The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides inverting logic. The SN74BCT29834 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE INPUTS OEB L H X OEA H L X CLR X H L H L H H X CLK X X No No X Ai of H's Odd Even NA X X X Odd Even Odd Even Bi of L's NA Odd Even X A NA B X OUTPUT AND I/O B A NA NA PARITY H L NA NA ERR NA H L H NC H L H NA FUNCTION
A data to B bus and generate parity B data to A bus and check parity Clear error-flag register Isolation§
H
H
X
Z
Z
Z
L
L
NA
NA
A
L H
A data to B bus and generate inverted parity
NA = not applicable, NC = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume the ERR output was previously high. § In this mode, the ERR output, when enabled, shows inverted parity of the A bus.
Copyright © 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 SEPTEMBER 1987 REVISED NOVEMBER 1993
functional logic diagram (positive logic)
A1 A8 8 EN 8x 8 8x 8 B1 B8
EN OEB
OEA
8
PARITY
8 MUX 1 1 1 1 G1 1D CLK CLR R C1 ERR 9 2k P
22
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74BCT29834 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 SEPTEMBER 1987 REVISED NOVEMBER 1993
error-flag waveforms
OEB H L H L
OEA
Bi + PARITY tsu th CLK tw CLR tPHL ERR tPLH tw tsu
Even Odd
H L
H L
H L ERROR-FLAG FUNCTION TABLE INPUTS CLR H H H CLK INTERNAL TO DEVICE POINT P H X L OUTPUT PRESTATE ERRn1 H L X OUTPUT FUNCTION ERR H L L Sample
L X X X H Clear ERRn1 represents the state of the ERR output before any changes at CLR, CLK, or point P.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
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