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Details, datasheet, quote on part number:SN74BCT8373NT
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Datasheet text preview:
SN74BCT8373 SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
SCBS471 JUNE 1990 REVISED JUNE 1994
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Member of the Texas Instruments SCOPE TM Family of Testability Products Octal Test-Integrated Circuit Functionally Equivalent to SN74F373 and SN74BCT373 in the Normal-Function Mode Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Test Operation Synchronous to Test Access Port (TAP) Implements Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V ) on TMS Pin SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs / Toggle Outputs Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
DW OR NT PACKAGE (TOP VIEW)
LE 1Q 2Q 3Q 4Q GND 5Q 6Q 7Q 8Q TDO TMS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE 1D 2D 3D 4D 5D VCC 6D 7D 8D TDI TCK
description
The SN74BCT8373 scan test device with octal D-type latches is a member of the Texas Instruments SCOPETM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, this device is functionally equivalent to the SN74F373 and SN74BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches. In the test mode, the normal operation of the SCOPETM octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990. Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN74BCT8373 is characterized for operation from 0°C to 70°C.
SCOPE is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
SN74BCT8373 SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
SCBS471 JUNE 1990 REVISED JUNE 1994
FUNCTION TABLE (normal mode, each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic symbol
SCAN SN74BCT8373 TDI TMS TCK-IN TCK-OUT OE LE 1D 2D 3D 4D 5D 6D 7D 8D 24 1 23 22 21 20 19 17 16 15 EN C1 1D 2 3 4 5 7 8 9 10 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q TDO 11 TDO
TDI TMS TCK
14 12 13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74BCT8373 SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
SCBS471 JUNE 1990 REVISED JUNE 1994
functional block diagram
Boundary-Scan Register
VCC OE 24 VCC LE 1
VCC 1D 23
C1 1D 2 1Q
One of Eight Channels
Bypass Register
Boundary- Control Register VCC TDI 14 VCC TMS 12 VCC TCK 13 TAP Controller Instruction Register
VCC 11 TDO
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
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