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Details, datasheet, quote on part number:SN74BCT899
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| Part: | SN74BCT899 |
| Category: | Logic => Bus Transceivers => CMOS/BiCMOS->ABT/BCT Family |
| Description: | 9-bit Latchable Transceiver With Parity Generator/checker |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74BCT899 datasheet File size : 108 kB |
| Request For quote: | Find where to buy SN74BCT899
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Datasheet text preview:
SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS253 JUNE 1992 REVISED NOVEMBER 1993
· · · · ·
State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions Simultaneously Generates and Checks Parity Packaged in Plastic Small-Outline Package
DW PACKAGE (TOP VIEW)
description
The SN74BCT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data buses in either direction. It has a current-sinking capability of 24 mA at the A bus and 64 mA at the B bus. The SN74BCT899 features independent latchenable (LEAB or LEBA) inputs, a select (SEL) input for ODD/EVEN parity, and separate error-signal (ERRA or ERRB) outputs for checking parity. The SN74BCT899 is characterized for operation from 0°C to 70°C.
ODD/EVEN ERRA LEAB A1 A2 A3 A4 A5 A6 A7 A8 APAR OEBA GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC OEAB B1 B2 B3 B4 B5 B6 B7 B8 BPAR LEBA SEL ERRB
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS253 JUNE 1992 REVISED NOVEMBER 1993
FUNCTION TABLE INPUTS OEAB H H OEBA H L SEL X L LEAB X X LEBA X H OPERATION OR FUNCTION OR FUNCTION Buses A and B are in the high-impedance state. Generates parity from B1 B8 based on ODD/EVEN. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B1 B8 based on ODD/EVEN. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B-latch data based on ODD/EVEN. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB. BPAR /B1 B8 APAR/A1 A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR /B1 B8 APAR/A1 A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from A1 A8 based on ODD/EVEN. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A1 A8 based on ODD/EVEN. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A-latch data based on ODD/EVEN. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA. APAR /A1 A8 BPAR/B1B8 feed-through mode. Generated parity checked against APAR and output as ERRA. APAR /A1 A8 BPAR/B1B8 feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Output to A bus and B bus PARITY FUNCTION TABLE INPUTS ODD/EVEN L L L L H H H OF INPUTS A1 A8 = H 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 APAR L L H H L L H OUTPUTS BPAR L H L H H L H ERRA H L L H L H H
H
L
L
H
H
H H H L
L L L H
L H H L
X X H H
L H H X
L
H
L
H
H
L L L L
H H H L
L H H X
L H H X
X X X X
H 1, 3, 5, 7 H L L If LE = H, current A1 A8 and APAR data is used. If LE = L, latched A1A8 and APAR data is used. This is the value of BPAR if SEL = L. If SEL = H, BPAR = APAR.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74BCT899 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS253 JUNE 1992 REVISED NOVEMBER 1993
logic diagram (positive logic)
ODD/EVEN SEL OEBA LEAB OEAB LEBA
9-Bit Transp. Latch A1 A2 A3 A4 A5 A6 A7 A8 APAR ERRA
9-Bit Buffer B1 B2 B3 B4 B5 B6 B7 B8 BPAR
Parity Generator
ERRB Parity Generator
9-Bit Buffer
9-Bit Transp. Latch
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . 0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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