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Details, datasheet, quote on part number:SN74BCT979
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| Part: | SN74BCT979 |
| Category: | Logic => Bus Transceivers => CMOS/BiCMOS->ABT/BCT Family |
| Description: | 9-bit Registered BTL Transceiver With Parity Generator/checker |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download SN74BCT979 datasheet File size : 138 kB |
| Request For quote: | Find where to buy SN74BCT979
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Datasheet text preview:
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A OCTOBER 1990 REVISED NOVEMBER 1993
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BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Support IEEE BTL Standard 1194.1-1991 Open-Collector B Port Drives Load Impedances as Low as 10 BTL Logic Level 1-V Bus Swing Reduces Power Consumption Latchable Transceiver With Output Sink of 24 mA at the A Bus and 100 mA at the B Bus Option to Generate and Check Parity or Feed-Through Data/Parity in Directions A to B or B to A Independent Latch Enables for A-to-B and B-to-A Directions Select Pin for ODD/EVEN Parity ERRA and ERRB Output Pins for Parity Checking Ability to Simultaneously Generate and Check Parity Packaged in 300-mil Plastic Shrink Small-Outline (DL) Package
DL PACKAGE (TOP VIEW)
VCC AI1 AO1 AI2 AO2 GND AI3 AO3 AI4 AO4 AI5 GND AO5 AI6 AO6 AI7 AO7 GND AI8 AO8 APARI APARO VCC LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
OEBA LEAB B1 GND GND B2 ERRA B3 GND GND B4 ODD/EVEN B5 SEL B6 GND GND B7 ERRB B8 GND GND BPAR OEAB
description
The SN74BCT979 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver, or it can generate/check parity from the 8-bit data bus in either direction. It has a guaranteed current-sinking capability of 24 mA at the A bus and 100 mA at the open-collector B bus. The SN74BCT979 features independent latch-enable (LEAB, LEBA) inputs for the A-to-B direction and the B-to-A direction, an ODD/EVEN input to select odd or even parity, and separate error-signal (ERRA, ERRB) outputs for checking parity. When communication between buses occurs, parity is generated and passed on to either bus as APARO or BPAR. Error detection of the parity generated from AI1 AI8 and B1 B8 can be checked by ERRA and ERRB, providing LEAB and LEBA are high and the mode select (SEL) is low. If SEL is high, the communication between buses is in a feed-through mode where parity is still generated and checked as ERRA and ERRB. The SN74BCT979 features open-collector driver outputs (B port) with a series Schottky diode to reduce capacitive loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately 1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of driving an equivalent dc load of as low as 10 . The transceiver has a precision threshold set by an internal bandgap reference to give accurate input thresholds over VCC and temperature variations. This transceiver is compatible with backplane transceiver logic (BTL) technology at significantly reduced power dissipation per channel. The SN74BCT979 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A OCTOBER 1990 REVISED NOVEMBER 1993
FUNCTION TABLE INPUTS OEAB H H H H H L L L L OEBA H L L L L H H H H SEL X L L H H L L H H LEAB X X X X X H L H L LEBA X H L H L X X X X OPERATION OR FUNCTION OR FUNCTION Isolation. AO1 AO8 /APARO are in the high-impedance state and B1 B8 /APAR are high. Parity is generated from B1 B8 data and output on APARO and is checked against BPAR and output on ERRB. Parity is generated from latched B1 B8 data and output on APARO and is checked against BPAR and output on ERRB. BPAR is output on APARO. Parity is generated from B1 B8 data, checked against BPAR, and output on ERRB. BPAR is output on APARO. Parity is generated from latched B1 B8 data, checked against BPAR, and output on ERRB. Parity is generated from AI1 AI8 data and output on BPAR and is checked against APARI and output on ERRA. Parity is generated from latched AI1 AI8 data and output on BPAR and is checked against APARI and output on ERRA. APARI is output on BPAR. Parity is generated from AI1 AI8 data, checked against APARI, and output on ERRA. APARI is output on BPAR. Parity is generated from latched AI1 AI8 data, checked against APARI, and output on ERRA.
L L X X X AO1 AO8 /APARO and B1 B8 /BPAR are active (high or low logic levels). Parity is generated from AI1 AI8 and from B1 B8 based on the level present at ODD/EVEN. Parity is checked (AI1 AI8 against APARI and B1 B8 against BPAR) based on the level present at ODD/EVEN (see parity function table). PARITY FUNCTION TABLE INPUTS OEAB L L L L L L L L L L L L L L L L H SEL L L L L L L L L H H H H H H H H X ODD/EVEN L L L L H H H H L L L L H H H H X OF INPUTS AI1 AI8 = H 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 X APARI L L H H L L H H L L H H L L H H X OUTPUTS BPAR L H L H H L H L L L H H L L H H H ERRA H L L H L H H L H L L H L H H L X
Parity functions for the A bus are shown. Parity functions for the B bus are similar, but use B1 B8 and BPAR as inputs and APARO and ERRB as outputs.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74BCT979 9-BIT REGISTERED BTL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
SCBS115A OCTOBER 1990 REVISED NOVEMBER 1993
LATCH FUNCTION TABLES INPUTS OUTPUT OEAB L L L H LEAB H H L X AI L H X X B L H Q0 H
INPUTS OEBA L L L LEBA H H L B L H X
OUTPUT AO L H Q0
H X X Z If LEAB = H, current AI1 AI8 and APARI data is used. If LEAB = L, latched AI1 AI8 and APARI data is used.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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