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Details, datasheet, quote on part number:SN74CB3Q16211DGGR
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Datasheet text preview:
SN74CB3Q16211 24 BIT SWITCH 2.5 V/3.3 V LOW VOLTAGE FET BUS SWITCH
SCDS167 - MAY 2004
D Member of the Texas Instruments D D D D D D D D D D D D D D D
D
Widebus Family High-Bandwidth Data Path (Up To 500 MHz) 5-V Tolerant I/Os with Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 5 Typical) Rail-to-Rail Switching on Data I/O Ports - 0-V to 5-V Switching With 3.3-V VCC - 0-V to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 4 pF Typical) Fast Switching Frequency (fOE = 20 MHz Max) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 1 mA Typical) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0-V to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating
DGG, DGV, OR DL PACKAGE (TOP VIEW)
NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12
NC - No internal connection
For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated Available under non-disclosure agreement (NDA) only
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCDS167 - MAY 2004
SN74CB3Q16211 24 BIT SWITCH 2.5 V/3.3 V LOW VOLTAGE FET BUS SWITCH
description/ordering information
The SN74CB3Q16211 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16211 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE Tube SSOP - DL -40°C to 85 C 85°C TSSOP - DGG TVSOP - DGV VFBGA - GQL Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CB3Q16211DL SN74CB3Q16211DLR SN74CB3Q16211DGGR SN74CB3Q16211DGVR SN74CB3Q16211GQLR CB3Q16211 CB3Q16211 BW211 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6 A B C D E F G H J K
terminal assignments
1 1A2 1A5 1A7 1A10 1A12 2A1 VCC 2A4 2A7 2A10 2 1A1 1A4 GND 1A8 1A11 2A2 GND 2A5 2A8 2A11 2A3 2A6 2A9 2A12 2B3 2B6 2B9 2B12 3 NC 1A3 1A6 1A9 4 1OE 1B2 1B5 1B8 5 2OE 1B3 GND 1B7 1B10 2B1 GND 2B5 2B8 2B11 6 1B1 1B4 1B6 1B9 1B11 1B12 2B2 2B4 2B7 2B10
NC - No internal connection
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CB3Q16211 24 BIT SWITCH 2.5 V/3.3 V LOW VOLTAGE FET BUS SWITCH
SCDS167 - MAY 2004
FUNCTION TABLE (each 12-bit bus switch) INPUT OE L H INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect
logic diagram (positive logic)
2 1A1 SW 54 1B1
14 1A12 SW
42 1B12
56 1OE
15 2A1 SW
41 2B1
28 2A12 SW
29 2B12
55 2OE
Pin numbers shown are for the DGG, DGV, and DL packages.
simplified schematic, each FET switch (SW)
A VCC B
Charge Pump
EN EN is the internal enable signal applied to the switch.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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