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Details, datasheet, quote on part number:SN74CB3T3384DWR
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Datasheet text preview:
SN74CB3T3384 10 BIT FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
D Output Voltage Translation Tracks VCC D Supports Mixed-Mode Signal Operation On
All Data I/O Ports - 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC - 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered-Up or Powered-Down Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Typical) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 40 µA Max)
D VCC Operating Range From 2.3 V to 3.6 V D Data I/Os Support 0 to 5-V Signaling Levels D D D D
(For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V/2.5-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, Memory Interleaving, Bus Isolation Ideal for Low-Power Portable Equipment
D D D D D D
D D
DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE
description/ordering information
ORDERING INFORMATION
TA SOIC - DW -40°C to 85°C SSOP (QSOP) - DBQ TSSOP - PW PACKAGE Tube Tape and reel Tape and reel Tube Tape and reel ORDERABLE PART NUMBER SN74CB3T3384DW SN74CB3T3384DWR SN74CB3T3384DBQR SN74CB3T3384PW SN74CB3T3384PWR KS384 CB3T3384 CB3T3384 TOP-SIDE MARKING
TVSOP - DGV Tape and reel SN74CB3T3384DGVR Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
SN74CB3T3384 10 BIT FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
description/ordering information (continued)
The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3384 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
VCC
5.5 V VCC VCC - 1 V IN OUT VCC VCC - 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC - 1 V, and less than or equal to 5.5 V, the output high voltage (VOH) level will be equal to approximately the VCC voltage level.
Figure 1. Typical DC-Voltage-Translation Characteristics The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE (each 5-bit bus switch) INPUT OE L H INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CB3T3384 10 BIT FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE BUS SWITCH WITH 5 V TOLERANT LEVEL SHIFTER
SCDS159B - OCTOBER 2003 - REVISED MARCH 2004
logic diagram (positive logic)
3 1A1 SW 2 1B1
11 1A5 SW
10 1B5
1 1OE
14 2A1 SW
15 2B1
22 2A5 SW
23 2B5
13 2OE
simplified schematic, each FET switch (SW)
Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. A VG Control Circuit B
EN EN is the internal enable signal applied to the switch.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
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