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Part: SN74CBT1G384DCK
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
Description: Single Fet Bus Switch
Company: Texas Instruments, Inc.
Datasheet: Download SN74CBT1G384DCK datasheet File size : 553 kB
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Datasheet text preview:
SN74CBT1G384 SINGLE FET BUS SWITCH
SCDS065B JULY 1998 REVISED JANUARY 2000
D D D
5- Switch Connection Between Two Ports TTL-Compatible Control Input Levels Packaged in Plastic Small-Outline Transistor (DBV, DCK) Packages
DBV OR DCK PACKAGE (TOP VIEW)
description
A B GND
1 2 3
5 4
VCC OE
The SN74CBT1G384 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high. The SN74CBT1G384 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUT OE L H FUNCTION A port = B port Disconnect
logic diagram (positive logic)
1 A 4 OE 2 B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
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1
SN74CBT1G384 SINGLE FET BUS SWITCH
SCDS065B JULY 1998 REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4 2 0.8 85 MAX 5.5 UNIT V V V °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC Ci Control input VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V or GND IO = 0, OE = VCC TYP at VCC = 4 V, VI = 0 VI = 2.4 V, II = 64 mA II = 30 mA II = 15 mA II = 15 mA VI = VCC or GND 3 4 14 5 5 20 7 7 MIN TYP MAX 1.2 ±1 1 UNIT V µA µA pF pF
Cio(OFF)
ron§
VI = 2.4 V, 10 15 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. § Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd¶ ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.35 5.5 1.6 VCC = 5 V ± 0.5 V MIN MAX 0.25 4.9 ns ns UNIT
tdis A or B 4.5 1 4.2 ns OE ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBT1G384 SINGLE FET BUS SWITCH
SCDS065B JULY 1998 REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 7 V (see Note B) tPZH TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
LOAD CIRCUIT
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The output is measured with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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