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Details, datasheet, quote on part number:SN74CBT3125PWLE
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Datasheet text preview:
SN74CBT3125 QUADRUPLE FET BUS SWITCH
SCDS021I MAY 1995 REVISED SEPTEMBER 2002
D
Standard '125-Type Pinout (D, DB, DGV, and PW Packages)
D D
RGY PACKAGE (TOP VIEW)
5- Switch Connection Between Two Ports TTL-Compatible Input Levels
DBQ PACKAGE (TOP VIEW)
D, DB, DGV, OR PW PACKAGE (TOP VIEW)
1OE
VCC
1OE 1A 1B 2OE 2A 2B GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4B 3OE 3A 3B
1
14 13 4OE 12 4A 11 4B 10 3OE 9 3A
1A 1B 2OE 2A 2B
2 3 4 5 6 7 8
NC 1OE 1A 1B 2OE 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4OE 4A 4B 3OE 3A 3B NC
GND
3B
NC No internal connection
description/ordering information
The SN74CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA QFN RGY SOIC D 40°C to 85°C SSOP DB SSOP (QSOP) DBQ TSSOP PW TVSOP DGV PACKAGE Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CBT3125RGYR SN74CBT3125D SN74CBT3125DR SN74CBT3125DBR SN74CBT3125DBQR SN74CBT3125PWR SN74CBT3125DGVR TOP-SIDE MARKING CU125 CBT3125 CU125 CU125 CU125 CU125
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
SN74CBT3125 QUADRUPLE FET BUS SWITCH
SCDS021I MAY 1995 REVISED SEPTEMBER 2002
logic diagram (positive logic)
2 1A 1 1OE 2A 5 6 2B 3 1B
4 2OE 9 3A 10 12 11 4B 13 8 3B
3OE 4A
4OE
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4 2 0.8 85 MAX 5.5 UNIT V V V °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBT3125 QUADRUPLE FET BUS SWITCH
SCDS021I MAY 1995 REVISED SEPTEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC ICC Ci Control inputs Control inputs VCC = 4 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron§ VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, OE = VCC VI = 2.4 V, VI = 0 II = 15 mA II = 64 mA II = 30 mA VI = VCC or GND Other inputs at VCC or GND 3 4 16 5 5 22 7 7 MIN TYP MAX 1.2 ±1 3 2.5 UNIT V µA µA mA pF pF
Cio(OFF)
VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd¶ ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.35 6 1.6 VCC = 5 V ± 0.5 V MIN MAX 0.25 5.4 ns ns UNIT
tdis A or B 5.1 1 4.7 ns OE ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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