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Details, datasheet, quote on part number:SN74CBT3306D
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Datasheet text preview:
SN74CBT3306 DUAL FET BUS SWITCH
SCDS016G MAY 1995 REVISED OCTOBER 2000
D D
5- Switch Connection Between Two Ports TTL-Compatible Input Levels
D OR PW PACKAGE (TOP VIEW)
description
The SN74CBT3306 dual FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high. ORDERING INFORMATION
TA SOIC D PACKAGE Tube Tape and reel
1OE 1A 1B GND
1 2 3 4
8 7 6 5
VCC 2OE 2B 2A
ORDERABLE PART NUMBER SN74CBT3306D SN74CBT3306DR
TOP-SIDE MARKING CU306
40°C to 85°C
TSSOP PW Tape and reel SN74CBT3306PWR CU306 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
logic diagram (positive logic)
1A 2 3 1B
1 1OE 5 2A 7 2OE 6 2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74CBT3306 DUAL FET BUS SWITCH
SCDS016G MAY 1995 REVISED OCTOBER 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature 40 4 2 0.8 85 MAX 5.5 UNIT V V V °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC ICC§ Ci Cio(OFF) Control inputs Control inputs VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron¶ VCC = 4.5 V TEST CONDITIONS II = 18 mA VI = 5.5 V or GND IO = 0, One input at 3.4 V, OE = VCC VI = 2.4 V, VI = 0 II = 15 mA II = 64 mA II = 30 mA VI = VCC or GND Other inputs at VCC or GND 3 4 14 5 5 20 7 7 MIN TYP MAX 1.2 ±1 3 2.5 UNIT V µA µA mA pF pF
VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74CBT3306 DUAL FET BUS SWITCH
SCDS016G MAY 1995 REVISED OCTOBER 2000
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.35 5.6 1.8 VCC = 5 V ± 0.5 V MIN MAX 0.25 5 ns ns UNIT
tdis A or B 4.6 1 4.3 ns OE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT
Output Control tPZL 3V Output Waveform 1 S1 at 7 V (see Note B) tPZH VOH Output Waveform 2 S1 at Open (see Note B)
3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
Input
1.5 V
1.5 V 0V
tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
tPHL 1.5 V VOL
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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